EZ80F91AZA50EG Zilog, EZ80F91AZA50EG Datasheet - Page 184

• Manufacturer Part Number: EZ80F91AZA50EG
• Description: IC ACCLAIM MCU 256KB 144LQFP
• Manufacturer: Zilog
• Series: eZ80® AcclaimPlus!™r

Specifications of EZ80F91AZA50EG

• Core Processor: Z8
• Core Size: 8-Bit
• Speed: 50MHz
• Connectivity: Ethernet, I²C, IrDA, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 144-LQFP
• Processor Series: EZ80F91x
• Core: eZ80
• Data Bus Width: 8 bit
• Data Ram Size: 16 KB
• Interface Type: I2C, IrDA, SPI
• Maximum Clock Frequency: 50 MHz
• Number Of Programmable I/os: 32
• Number Of Timers: 4
• Operating Supply Voltage: 3 V to 3.6 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: eZ80F910300ZCOG
• Minimum Operating Temperature: - 40 C
• For Use With: 269-4712 - KIT DEV ENCORE 32 SERIES269-4671 - BOARD ZDOTS SBC Z80ACCLAIM PLUS269-4561 - KIT DEV FOR EZ80F91 W/C-COMPILER269-4560 - KIT DEV FOR EZ80F91 W/C-COMPILER
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details
• Other names: 269-4563

PS027001-0707
UART Functional Description
UART Functions
The UART Baud Rate Generator (BRG) creates the clock for the serial transmit and
receive functions. The UART module supports all of the various options in the asynchro-
nous transmission and reception protocol including:
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The UART contains 16-byte-deep FIFOs in each direction. The FIFOs are enabled or dis-
abled by the application. The receive FIFO features trigger-level detection logic, which
enables the CPU to block-transfer data bytes from the receive FIFO.
The UART function implements:
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UART Transmitter
The transmitter block controls the data transmitted on the TxD output. It implements the
FIFO, access via the UARTx_THR register, the transmit shift register, the parity generator,
and control logic for the transmitter to control parameters for the asynchronous communi-
cations protocol.
The UARTx_THR is a Write Only register. The CPU writes the data byte to be transmitted
into this register. In FIFO mode, up to 16 data bytes are written via the UARTx_THR reg-
ister. The data byte from the FIFO is transferred to the transmit shift register at the appro-
priate time and transmitted via TxD output. After SYNC_RESET, the UARTx_THR
register is empty. Therefore, the Transmit Holding Register Empty (THRE) bit (bit 5 of
the UARTX_LSR register) is 1. An interrupt is sent to the CPU if interrupts are enabled.
The CPU resets this interrupt by loading data into the UARTx_THR register, which clears
the transmitter interrupt.
The transmit shift register places the byte to be transmitted on the TxD signal serially. The
least-significant bit of the byte to be transmitted is shifted out first and the most-significant
bit is shifted out last. The control logic within the block adds the asynchronous communi-
cations protocol bits to the data byte being transmitted. The transmitter block obtains the
5- to 9-bit transmit/receive
Start bit generation and detection
Parity generation and detection
Stop bit generation and detection
Break generation and detection
The transmitter and associated control logic
The receiver and associated control logic
The modem interface and associated logic
Universal Asynchronous Receiver/Transmitter
Product Specification
eZ80F91 ASSP
176