EZ80F91AZA50EG Zilog, EZ80F91AZA50EG Datasheet - Page 250

• Manufacturer Part Number: EZ80F91AZA50EG
• Description: IC ACCLAIM MCU 256KB 144LQFP
• Manufacturer: Zilog
• Series: eZ80® AcclaimPlus!™r

Specifications of EZ80F91AZA50EG

• Core Processor: Z8
• Core Size: 8-Bit
• Speed: 50MHz
• Connectivity: Ethernet, I²C, IrDA, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 144-LQFP
• Processor Series: EZ80F91x
• Core: eZ80
• Data Bus Width: 8 bit
• Data Ram Size: 16 KB
• Interface Type: I2C, IrDA, SPI
• Maximum Clock Frequency: 50 MHz
• Number Of Programmable I/os: 32
• Number Of Timers: 4
• Operating Supply Voltage: 3 V to 3.6 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: eZ80F910300ZCOG
• Minimum Operating Temperature: - 40 C
• For Use With: 269-4712 - KIT DEV ENCORE 32 SERIES269-4671 - BOARD ZDOTS SBC Z80ACCLAIM PLUS269-4561 - KIT DEV FOR EZ80F91 W/C-COMPILER269-4560 - KIT DEV FOR EZ80F91 W/C-COMPILER
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details
• Other names: 269-4563

PS027001-0707
ZDA
ZCL
Operation of the eZ80F91 Device during ZDI Break Points
Bus Requests During ZDI Debug Mode
ZDI Address
lsb of
a read operation at 0x00 increments the PC to 0x02. To read the next byte, the PC must be
decremented by one.
ZDI Block Read
A block Read operation is initiated in the same manner as a single-byte Read; however,
the ZDI master continues to clock in the next byte from the ZDI slave as the ZDI slave
continues to output data. The ZDI register address counter increments with each Read. If
the ZDI register address reaches the end of the Read Only ZDI register address space
(
If the ZDI forces the CPU to break, only the CPU suspends operation. The system clock
continues to operate and drive other peripherals. Those peripherals that operate autono-
mously from the CPU continues to operate, if so enabled. For example, the Watchdog
Timer and Programmable Reload Timers continue to count during a ZDI break point.
When using the ZDI interface, any Write or Read operations of peripheral registers in the
I/O address space produces the same effect as Read or Write operations using the CPU. As
many register Read/Write operations exhibit secondary effects, such as clearing flags or
causing operations to commence, the effects of the Read/Write operations during a ZDI
break must be taken into consideration.
The ZDI block on the eZ80F91 device allows an external device to take control of the
address and data bus while the eZ80F91 device is in DEBUG mode. ZDI_BUSACK_EN
causes ZDI to allow or prevent acknowledgement of bus requests by external peripherals.
The bus acknowledge occurs only at the end of the current ZDI operation (indicated by a
High during the single-bit byte separator). The default reset condition is for bus acknowl-
A0
7
20h
), the address stops incrementing.
Read
8
Byte Separator
Single-Bit
0/1
Figure 56. ZDI Block Data Read Timing
9
of DATA
Byte 1
msb
D7
1
D6
2
D5
3
Figure 56
ZDI Data Bytes
D1
7
of DATA
Byte 1
illustrates the ZDI’s block Read timing.
D0
lsb
8
Byte Separator
Single-Bit
0/1
9
of DATA
Byte 2
msb
D7
Product Specification
1
Zilog Debug Interface
D6
2
eZ80F91 ASSP
1
9
242