EZ80F91AZA50EG Zilog, EZ80F91AZA50EG Datasheet - Page 333

• Manufacturer Part Number: EZ80F91AZA50EG
• Description: IC ACCLAIM MCU 256KB 144LQFP
• Manufacturer: Zilog
• Series: eZ80® AcclaimPlus!™r

Specifications of EZ80F91AZA50EG

• Core Processor: Z8
• Core Size: 8-Bit
• Speed: 50MHz
• Connectivity: Ethernet, I²C, IrDA, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 144-LQFP
• Processor Series: EZ80F91x
• Core: eZ80
• Data Bus Width: 8 bit
• Data Ram Size: 16 KB
• Interface Type: I2C, IrDA, SPI
• Maximum Clock Frequency: 50 MHz
• Number Of Programmable I/os: 32
• Number Of Timers: 4
• Operating Supply Voltage: 3 V to 3.6 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: eZ80F910300ZCOG
• Minimum Operating Temperature: - 40 C
• For Use With: 269-4712 - KIT DEV ENCORE 32 SERIES269-4671 - BOARD ZDOTS SBC Z80ACCLAIM PLUS269-4561 - KIT DEV FOR EZ80F91 W/C-COMPILER269-4560 - KIT DEV FOR EZ80F91 W/C-COMPILER
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details
• Other names: 269-4563

Table 211. EMAC Receive High Boundary Pointer Register—High Byte (EMAC_RHBP_H = 0048h)
Table 212. EMAC Receive Read Pointer Register—Low Byte
PS027001-0707
Bit
Reset
CPU Access
Note: R = Read Only, R/W = Read/Write
Bit
Position
[7:0]
EMAC_RHBP_H
Note: *Bits 7:5 are not used by the EMAC; these bits return 000 upon reset.
Bit
Reset
CPU Access
Note: R = Read Only, R/W = Read/Write
Bit
Position
[7:0]
EMAC_RRP_L
EMAC Receive Read Pointer Register—Low and High Bytes
The Receive Read Pointer Register must be initialized to the EMAC_BP value (start of the
Receive buffer). This register points to where the next Receive packet is read from. The
EMAC_BP[12:5] is loaded into this register whenever the EMAC_RST [(HRRFN) is set
to 1. The RxDMA block uses the Emac_Rrp[12:5] to compare to EmacRwp[12:5] for
determining how many buffers remain. The result equates to the EmacBlksLeft register.
See
Value
00h–FFh These bits represent the High byte of the 2 byte EMAC
Value
00h–FFh These bits represent the Low byte of the 2 byte EMAC
Table 212
R/W
R
7
1
7
0
Description
Receive High Boundary Pointer value, {EMAC_RHBP_H,
EMAC_RHBP_L}. Bit 7 is bit 15 (msb) of the 16 bit value. Bit
0 is bit 8 of the 16 bit value.
Description
Receive Read Pointer value, {EMAC_RRP_H,
EMAC_RRP_L}. Bit 7 is bit 7 of the 16 bit value. Bit 0 is bit 0
(lsb) of the 16 bit value.
and
R/W
Table 213
R
6
1
6
0
R/W
R
5
0
5
0
on page 326.
R/W
R
4
0
4
0
R/W
R
3
0
3
0
R/W
R
2
0
2
0
(EMAC_RRP_L = 0049h)
R/W
Ethernet Media Access Controller
R
1
0
1
0
Product Specification
R/W
R
0
0
0
0
eZ80F91 ASSP
325