EZ80F91AZA50EG Zilog, EZ80F91AZA50EG Datasheet - Page 44

• Manufacturer Part Number: EZ80F91AZA50EG
• Description: IC ACCLAIM MCU 256KB 144LQFP
• Manufacturer: Zilog
• Series: eZ80® AcclaimPlus!™r

Specifications of EZ80F91AZA50EG

• Core Processor: Z8
• Core Size: 8-Bit
• Speed: 50MHz
• Connectivity: Ethernet, I²C, IrDA, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 144-LQFP
• Processor Series: EZ80F91x
• Core: eZ80
• Data Bus Width: 8 bit
• Data Ram Size: 16 KB
• Interface Type: I2C, IrDA, SPI
• Maximum Clock Frequency: 50 MHz
• Number Of Programmable I/os: 32
• Number Of Timers: 4
• Operating Supply Voltage: 3 V to 3.6 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: eZ80F910300ZCOG
• Minimum Operating Temperature: - 40 C
• For Use With: 269-4712 - KIT DEV ENCORE 32 SERIES269-4671 - BOARD ZDOTS SBC Z80ACCLAIM PLUS269-4561 - KIT DEV FOR EZ80F91 W/C-COMPILER269-4560 - KIT DEV FOR EZ80F91 W/C-COMPILER
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details
• Other names: 269-4563

Table 3. Register Map (Continued)
PS027001-0707
Address
(hex)
00C4
00C5
00C6
00C7
I<SuperscriptBold>2C
00C8
00C9
00CA
00CB
General-Purpose Input/Output Ports
00CE
00CF
00CC
00CD
Universal Asynchronous Receiver/Transmitter 1 (UART1)
00D0
00D1
00D2
00D3
Universal Asynchronous Receiver/Transmitter 0 (UART0)
00D4
00D5
Mnemonic
UART0_MCTL
UART0_LSR
UART0_MSR
UART0_SPR
I2C_SAR
I2C_XSAR
I2C_DR
I2C_CTL
PC_ALT0
PD_ALT0
I2C_SR
I2C_CCR
I2C_SRR
UART1_RBR
UART1_THR
UART1_BRG_L
UART1_IER
UART1_BRG_H
UART1_IIR
UART1_FCTL
UART1_LCTL
UART1_MCTL
UART1_LSR
Name
UART 0 Modem Control Register
UART 0 Line Status Register
UART 0 Modem Status Register
UART 0 Scratch Pad Register
I
I
I
I
Port C Alternate Register 0
Port D Alternate Register 0
I
I
I
UART 1 Receive Buffer Register
UART 1 Transmit Holding Register
UART 1 Baud Rate Generator
Register—Low Byte
UART 1 Interrupt Enable Register
UART 1 Baud Rate Generator
Register—High Byte
UART 1 Interrupt Identification Register
UART 1 FIFO Control Register
UART 1 Line Control Register
UART 1 Modem Control Register
UART 1 Line Status Register
2
2
2
2
2
2
2
C Slave Address Register
C Extended Slave Address Register
C Data Register
C Control Register
C Status Register
C Clock Control Register
C Software Reset Register
Reset
(hex)
XX
XX
XX
XX
00
60
00
00
00
00
00
00
00
F8
00
02
00
00
01
00
00
00
60
Product Specification
Access
eZ80F91 ASSP
CPU
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
W
W
W
W
W
W
R
R
R
R
R
Register Map
Page
191
192
194
195
226
226
227
229
230
232
233
184
184
182
185
183
186
187
188
191
192
No
56
56
36