EZ80F91AZA50EG Zilog, EZ80F91AZA50EG Datasheet - Page 208

• Manufacturer Part Number: EZ80F91AZA50EG
• Description: IC ACCLAIM MCU 256KB 144LQFP
• Manufacturer: Zilog
• Series: eZ80® AcclaimPlus!™r

Specifications of EZ80F91AZA50EG

• Core Processor: Z8
• Core Size: 8-Bit
• Speed: 50MHz
• Connectivity: Ethernet, I²C, IrDA, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 144-LQFP
• Processor Series: EZ80F91x
• Core: eZ80
• Data Bus Width: 8 bit
• Data Ram Size: 16 KB
• Interface Type: I2C, IrDA, SPI
• Maximum Clock Frequency: 50 MHz
• Number Of Programmable I/os: 32
• Number Of Timers: 4
• Operating Supply Voltage: 3 V to 3.6 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: eZ80F910300ZCOG
• Minimum Operating Temperature: - 40 C
• For Use With: 269-4712 - KIT DEV ENCORE 32 SERIES269-4671 - BOARD ZDOTS SBC Z80ACCLAIM PLUS269-4561 - KIT DEV FOR EZ80F91 W/C-COMPILER269-4560 - KIT DEV FOR EZ80F91 W/C-COMPILER
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details
• Other names: 269-4563

Table 109. GPIO Mode Selection when using the IrDA Encoder/Decoder
PS027001-0707
GPIO Port D
Bits
PD0
PD1
PD2–PD7
Jitter
Infrared Encoder/Decoder Signal Pins
Loopback Testing
If this equation results in a value less than one, MIN_PULSE must be set to 0x0h which
enables edge detection and ensures that valid pulses wider than W
field's maximum setting of 0xFh supports a W
Due to the inherent sampling of the received IR_RxD signal by the Bit Rate Clock, some
jitter is expected on the first bit in any sequence of data. However, all subsequent bits in
the received data stream are a fixed 16 clock periods wide.
The endec signal pins, IR_TxD and IR_RxD, are multiplexed with General Purpose
Input/Output (GPIO) pins. These GPIO pins must be configured for alternate function
operation for the endec to operate.
The remaining six UART0 pins, CTS0, DCD0, DSR0, DTR0, RTS and RI0, are not
required for use with the endec. The UART0 modem status interrupt must be disabled to
prevent unwanted interrupts from these pins. The GPIO pins corresponding to these six
unused UART0 pins are used for inputs, outputs, or interrupt sources. Recommended
GPIO Port D control register settings are provided in
Input/Output
Both internal and external loopback testing is accomplished with the endec on the eZ80F91
device. Internal loopback testing is enabled by setting the LOOP_BACK bit to 1. During
internal loopback, the IR_TxD output signal is inverted and connected on-chip to the
IR_RxD input. External loopback testing of the off-chip IrDA transceiver is accomplished
by transmitting data from the UART while the receiver is enabled (IR_RxEN set to 1).
Allowable GPIO
Port Mode
7
7
Any other than GPIO Mode 7
(1, 2, 3, 4, 5, 6, 8, or 9)
on page 49 for additional information on setting the GPIO Port modes.
Allowable Port Mode Functions
Alternate Function
Alternate Function
Output, Input, Open-Drain, Open-Source, Level-
sensitive Interrupt Input, or Edge-Triggered Interrupt
Input
min
of 1.25 us when F
Table
109. See
Product Specification
min
Infrared Encoder/Decoder
sys
General Purpose
are accepted. The
is 50 MHz.
eZ80F91 ASSP
200