EZ80F91AZA50EG Zilog, EZ80F91AZA50EG Datasheet - Page 319

• Manufacturer Part Number: EZ80F91AZA50EG
• Description: IC ACCLAIM MCU 256KB 144LQFP
• Manufacturer: Zilog
• Series: eZ80® AcclaimPlus!™r

Specifications of EZ80F91AZA50EG

• Core Processor: Z8
• Core Size: 8-Bit
• Speed: 50MHz
• Connectivity: Ethernet, I²C, IrDA, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 144-LQFP
• Processor Series: EZ80F91x
• Core: eZ80
• Data Bus Width: 8 bit
• Data Ram Size: 16 KB
• Interface Type: I2C, IrDA, SPI
• Maximum Clock Frequency: 50 MHz
• Number Of Programmable I/os: 32
• Number Of Timers: 4
• Operating Supply Voltage: 3 V to 3.6 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: eZ80F910300ZCOG
• Minimum Operating Temperature: - 40 C
• For Use With: 269-4712 - KIT DEV ENCORE 32 SERIES269-4671 - BOARD ZDOTS SBC Z80ACCLAIM PLUS269-4561 - KIT DEV FOR EZ80F91 W/C-COMPILER269-4560 - KIT DEV FOR EZ80F91 W/C-COMPILER
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details
• Other names: 269-4563

Table 190. EMAC_IPGT Non-Back-to-Back Settings for Full- /Half-Duplex Modes
PS027001-0707
Note: *The IEEE 802.3, 802.3(u) minimum values are shaded.
IPGR2[6:0]
Clock Period = 40 ns
MII, RMII/SMII, PMD
*12h
00h
10h
20h
40h
7Fh
Table 191. EMAC Interpacket Gap Register
Bit
Reset
CPU Access
Note: R = Read Only; R/W = Read/Write
(100 Mbps)
A non-back-to-back Transmit IPG is determined by the following formula:
The difference in values between
asynchronous nature of the Carrier Sense (CRS). The CRS must undergo a 2-clock
synchronization before the internal Tx state machine detects it. This synchronization
equates to a 6-clock intrinsic delay between packets instead of the 3-clock intrinsic delay
in the back-to-back packet mode. More information covering this topic is found in the
IEEE 802.3/4.2.3.2.1 Carrier Deference section.
EMAC Interpacket Gap Register
The EMAC Interpacket Gap (IPG) is a programmable field representing the IPG between
back-to-back packets. It is the IPG parameter used in FULL-DUPLEX and HALF-
DUPLEX modes between back-to-back packets. Set this field to the appropriate number
of IPG bytes. The default setting of
Mbps) or 9.6 μs (at 10 Mbps). See
Interpacket
0.24 µs
0.88 µs
0.96 µs
1.52 µs
2.80 µs
5.32 µs
Gap
IPGR2[6:0]
(6 clocks + IPGR2 clocks) * clock period = IPG
Clock Period = 400 ns
7Fh
00h
10h
12h
20h
40h
R
7
0
MII, RMII/SMII
(10 Mbps)
R/W
6
0
Interpacket
15.2 µs
28.0 µs
53.2 µs
2.4 µs
8.8 µs
9.6 µs
Table 189
Gap
R/W
Table
15h
5
0
represents the minimum IPG of 0.96 µs (at 100
191.
(EMAC_IPGT = 002Dh)
R/W
on page 310 and
4
1
IPGR2[6:0]
Clock Period = 100 ns
5Ah
7Fh
00h
10h
20h
40h
R/W
ENDEC Mode
3
0
(10 Mbps)
R/W
Ethernet Media Access Controller
Interpacket
2
1
Table 190
13.3 µs
0.6 µs
2.2 µs
3.8 µs
9.6 µs
7.0 µs
Gap
Product Specification
R/W
1
0
is due to the
eZ80F91 ASSP
R/W
0
1
311