EZ80F91AZA50EG Zilog, EZ80F91AZA50EG Datasheet - Page 229

• Manufacturer Part Number: EZ80F91AZA50EG
• Description: IC ACCLAIM MCU 256KB 144LQFP
• Manufacturer: Zilog
• Series: eZ80® AcclaimPlus!™r

Specifications of EZ80F91AZA50EG

• Core Processor: Z8
• Core Size: 8-Bit
• Speed: 50MHz
• Connectivity: Ethernet, I²C, IrDA, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 144-LQFP
• Processor Series: EZ80F91x
• Core: eZ80
• Data Bus Width: 8 bit
• Data Ram Size: 16 KB
• Interface Type: I2C, IrDA, SPI
• Maximum Clock Frequency: 50 MHz
• Number Of Programmable I/os: 32
• Number Of Timers: 4
• Operating Supply Voltage: 3 V to 3.6 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: eZ80F910300ZCOG
• Minimum Operating Temperature: - 40 C
• For Use With: 269-4712 - KIT DEV ENCORE 32 SERIES269-4671 - BOARD ZDOTS SBC Z80ACCLAIM PLUS269-4561 - KIT DEV FOR EZ80F91 W/C-COMPILER269-4560 - KIT DEV FOR EZ80F91 W/C-COMPILER
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details
• Other names: 269-4563

Table 120. I
PS027001-0707
Code
28h
30h
38h
I
Data byte transmitted,
ACK received
Data byte transmitted,
ACK not received
Arbitration lost
2
2
C State
C Master Transmit Status Codes For Data Bytes
If a repeated START condition is transmitted, the status code is
After each data byte is transmitted, the IFLG is set to 1 and one of the status codes listed in
Table 120
When all bytes are transmitted, the ASSP must write a 1 to the STP bit in the I2C_CTL
register. The I
state.
Master Receive
In MASTER RECEIVE mode, the I
transmitter.
After the START condition is transmitted, the IFLG bit is 1 and the status code
loaded into the I2C_SR register. The I2C_DR register must be loaded with the slave
address (or the first part of a 10-bit slave address), with the lsb set to 1 to signify a Read.
The IFLG bit must be cleared to 0 as a prompt for the transfer to continue.
When the 7-bit slave address (or the first part of a 10-bit address) and the Read bit are
transmitted, the IFLG bit is set and one of the status codes listed in
is loaded into the I2C_SR register.
is loaded into the I2C_SR register.
2
C then transmits a STOP condition, clears the STP bit and returns to an idle
ASSP Response
Write byte to data,
clear IFLG
Or set STA, clear IFLG
Or set STP, clear IFLG
Or set STA & STP,
clear IFLG
Same as code 28h
Clear IFLG
Or set STA, clear IFLG
2
C receives a number of bytes from a slave
Next I
Transmit repeated START
Transmit data byte,
receive ACK
Transmit STOP
Transmit START then STOP
Same as code 28h
Return to idle
Transmit START when bus free
2
C Action
10h
Product Specification
Table 121
instead of
I
2
C Serial I/O Interface
eZ80F91 ASSP
on page 222
08h
08h
.
is
221