EZ80F91AZA50EG Zilog, EZ80F91AZA50EG Datasheet - Page 213
EZ80F91AZA50EG
Manufacturer Part Number
EZ80F91AZA50EG
Description
IC ACCLAIM MCU 256KB 144LQFP
Manufacturer
Zilog
Series
eZ80® AcclaimPlus!™r
Datasheet
1.EZ80F91AZA50SG.pdf
(387 pages)
Specifications of EZ80F91AZA50EG
Core Processor
Z8
Core Size
8-Bit
Speed
50MHz
Connectivity
Ethernet, I²C, IrDA, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
32
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Oscillator Type
Internal
Operating Temperature
-40°C ~ 105°C
Package / Case
144-LQFP
Processor Series
EZ80F91x
Core
eZ80
Data Bus Width
8 bit
Data Ram Size
16 KB
Interface Type
I2C, IrDA, SPI
Maximum Clock Frequency
50 MHz
Number Of Programmable I/os
32
Number Of Timers
4
Operating Supply Voltage
3 V to 3.6 V
Maximum Operating Temperature
+ 105 C
Mounting Style
SMD/SMT
Development Tools By Supplier
eZ80F910300ZCOG
Minimum Operating Temperature
- 40 C
For Use With
269-4712 - KIT DEV ENCORE 32 SERIES269-4671 - BOARD ZDOTS SBC Z80ACCLAIM PLUS269-4561 - KIT DEV FOR EZ80F91 W/C-COMPILER269-4560 - KIT DEV FOR EZ80F91 W/C-COMPILER
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Data Converters
-
Lead Free Status / Rohs Status
Details
Other names
269-4563
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
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Table 111. SPI Clock Phase and Clock Polarity Operation
PS027001-0707
CPHA
(CPHA bit = 0) Data Out
(CPHA bit = 1) Data Out
0
0
1
1
ENABLE (To Slave)
SCK (CPOL bit = 0)
SCK (CPOL bit = 1)
Sample Input
Sample Input
CPOL
master, the SCK pin becomes an input on a slave device. The SPI contains an internal
divide-by-two clock divider. In MASTER mode, the SPI serial clock is one-half the fre-
quency of the clock signal created by the SPI’s Baud Rate Generator.
As demonstrated in
using the clock polarity (CPOL) and clock phase CPHA control bits in the SPI Control
register. See
with the identical timing, CPOL, and CPHA. The master device always places data on the
MOSI line a half-cycle before the clock edge (SCK signal), for the slave device to latch
the data.
0
1
0
1
Transmit
SPI Control Register
Falling
Falling
Rising
Rising
Edge
SCK
MSB
MSB
Figure 42
1
Figure 42. SPI Timing
SCK
Receive
Edge
6
Falling
Falling
Rising
Rising
6
2
and
Number of Cycles on the SCK Signal
5
on page 210. Both the master and slave must operate
Table
5
3
111, four possible timing relations are chosen by
4
State
SCK
High
High
Low
Low
Idle
4
4
3
3
5
Characters?
2
Between
SS High
Yes
Yes
No
No
2
6
Product Specification
1
Serial Peripheral Interface
1
7
eZ80F91 ASSP
LSB
LSB
8
205
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