EZ80F91AZA50EG Zilog, EZ80F91AZA50EG Datasheet - Page 331

• Manufacturer Part Number: EZ80F91AZA50EG
• Description: IC ACCLAIM MCU 256KB 144LQFP
• Manufacturer: Zilog
• Series: eZ80® AcclaimPlus!™r

Specifications of EZ80F91AZA50EG

• Core Processor: Z8
• Core Size: 8-Bit
• Speed: 50MHz
• Connectivity: Ethernet, I²C, IrDA, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 144-LQFP
• Processor Series: EZ80F91x
• Core: eZ80
• Data Bus Width: 8 bit
• Data Ram Size: 16 KB
• Interface Type: I2C, IrDA, SPI
• Maximum Clock Frequency: 50 MHz
• Number Of Programmable I/os: 32
• Number Of Timers: 4
• Operating Supply Voltage: 3 V to 3.6 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: eZ80F910300ZCOG
• Minimum Operating Temperature: - 40 C
• For Use With: 269-4712 - KIT DEV ENCORE 32 SERIES269-4671 - BOARD ZDOTS SBC Z80ACCLAIM PLUS269-4561 - KIT DEV FOR EZ80F91 W/C-COMPILER269-4560 - KIT DEV FOR EZ80F91 W/C-COMPILER
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details
• Other names: 269-4563

Table 207. EMAC Boundary Pointer Register—Low Byte
Table 208. EMAC Boundary Pointer Register—High Byte
PS027001-0707
Bit
Reset
CPU Access
Note: R = Read Only, R/W = Read/Write.
Bit
Position
[7:0]
EMAC_BP_L
Bit
Reset
CPU Access
Note: R = Read Only, R/W = Read/Write.
Bit
Position
[7:0]
EMAC_BP_H
EMAC Boundary Pointer Register—Low and High Bytes
The Boundary Pointer is set to the start of the Receive buffer (end of Transmit buffer +1)
in EMAC shared memory. This pointer is 24 bits and determined by {RAM_ADDR_U,
EMAC_BP_H, EMAC_BP_L}. The upper 3 bits of the EMAC_BP_H register are hard-
wired inside the eZ80F91 device to locate the base of EMAC shared memory. The last 5
bits of the EMAC_BP_L register value are hard-wired to keep the addressing aligned to
a 32 byte boundary. See
EMAC Boundary Pointer Register—Upper Byte
The EMAC Boundary Pointer Register maps directly to the RAM_ADDR_U register
within the eZ80F91 device. This register value is Read Only. See
Value
00h–FFh These bits represent the Low byte of the 3 byte EMAC
Value
00h–FFh These bits represent the High byte of the 3 byte EMAC
R/W
Description
Boundary Pointer value, {EMAC_BP_U, EMAC_BP_H,
EMAC_BP_L}. Bit 7 is bit 15 of the 24 bit value. Bit 0 is bit 8 of
the 24 bit value.
Description
Boundary Pointer value, {EMAC_BP_U, EMAC_BP_H,
EMAC_BP_L}. Bit 7 is bit 7 of the 24 bit value. Bit 0 is bit 0 of
the 24 bit value.
R
7
0
1
15:13
R/W
R
6
0
1
Table 207
R/W
R
5
0
0
R/W
and
R
4
0
0
Table
R/W
R
3
0
0
208.
(EMAC_BP_L = 0044h)
(EMAC_BP_H = 0045h)
12:8
R/W
R
2
0
0
R/W
Ethernet Media Access Controller
R
1
0
0
Product Specification
Table 209
R/W
R
0
0
0
eZ80F91 ASSP
on page 324.
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