EZ80F91AZA50EG Zilog, EZ80F91AZA50EG Datasheet - Page 193

• Manufacturer Part Number: EZ80F91AZA50EG
• Description: IC ACCLAIM MCU 256KB 144LQFP
• Manufacturer: Zilog
• Series: eZ80® AcclaimPlus!™r

Specifications of EZ80F91AZA50EG

• Core Processor: Z8
• Core Size: 8-Bit
• Speed: 50MHz
• Connectivity: Ethernet, I²C, IrDA, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 144-LQFP
• Processor Series: EZ80F91x
• Core: eZ80
• Data Bus Width: 8 bit
• Data Ram Size: 16 KB
• Interface Type: I2C, IrDA, SPI
• Maximum Clock Frequency: 50 MHz
• Number Of Programmable I/os: 32
• Number Of Timers: 4
• Operating Supply Voltage: 3 V to 3.6 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: eZ80F910300ZCOG
• Minimum Operating Temperature: - 40 C
• For Use With: 269-4712 - KIT DEV ENCORE 32 SERIES269-4671 - BOARD ZDOTS SBC Z80ACCLAIM PLUS269-4561 - KIT DEV FOR EZ80F91 W/C-COMPILER269-4560 - KIT DEV FOR EZ80F91 W/C-COMPILER
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details
• Other names: 269-4563

Table 98. UART Interrupt Enable Registers
PS027001-0707
Bit
Reset
CPU Access
Note: R/W = Read/Write.
Bit
Position
[7:5]
4
TCIE
3
MIIE
2
LSIE
1
TIE
0
RIE
Value
000
0
1
0
1
0
1
0
1
0
1
Description
Reserved
Transmission complete interrupt is disabled
Transmission complete interrupt is generated when both the transmit hold
register and the transmit shift register are empty
Modem interrupt on edge detect of status inputs is disabled.
Modem interrupt on edge detect of status inputs is enabled.
Line status interrupt is disabled.
Line status interrupt is enabled for receive data errors: incorrect parity bit
received, framing error, overrun error, or break detection.
Transmit interrupt is disabled.
Transmit interrupt is enabled. Interrupt is generated when the transmit
FIFO/buffer is empty indicating no more bytes available for transmission.
Receive interrupt is disabled.
Receive interrupt and receiver time-out interrupt are enabled. Interrupt is
generated if the FIFO/buffer contains data ready to be read or if the
receiver times out.
R/W
7
0
R/W
6
0
R/W
(UART0_IER = 00C1h, UART1_IER = 00D1h)
5
0
R/W
4
0
Universal Asynchronous Receiver/Transmitter
R/W
3
0
R/W
Product Specification
2
0
eZ80F91 ASSP
R/W
1
0
R/W
0
0
185