EZ80F91AZA50EG Zilog, EZ80F91AZA50EG Datasheet - Page 156
EZ80F91AZA50EG
Manufacturer Part Number
EZ80F91AZA50EG
Description
IC ACCLAIM MCU 256KB 144LQFP
Manufacturer
Zilog
Series
eZ80® AcclaimPlus!™r
Datasheet
1.EZ80F91AZA50SG.pdf
(387 pages)
Specifications of EZ80F91AZA50EG
Core Processor
Z8
Core Size
8-Bit
Speed
50MHz
Connectivity
Ethernet, I²C, IrDA, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
32
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Oscillator Type
Internal
Operating Temperature
-40°C ~ 105°C
Package / Case
144-LQFP
Processor Series
EZ80F91x
Core
eZ80
Data Bus Width
8 bit
Data Ram Size
16 KB
Interface Type
I2C, IrDA, SPI
Maximum Clock Frequency
50 MHz
Number Of Programmable I/os
32
Number Of Timers
4
Operating Supply Voltage
3 V to 3.6 V
Maximum Operating Temperature
+ 105 C
Mounting Style
SMD/SMT
Development Tools By Supplier
eZ80F910300ZCOG
Minimum Operating Temperature
- 40 C
For Use With
269-4712 - KIT DEV ENCORE 32 SERIES269-4671 - BOARD ZDOTS SBC Z80ACCLAIM PLUS269-4561 - KIT DEV FOR EZ80F91 W/C-COMPILER269-4560 - KIT DEV FOR EZ80F91 W/C-COMPILER
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Data Converters
-
Lead Free Status / Rohs Status
Details
Other names
269-4563
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
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- Download datasheet (5Mb)
PS027001-0707
Note:
PWM Master Mode
Modification of Edge Transition Values
Table 71. Example: Multi-PWM Addressing
In PWM Master mode, the pair of output signals generated from the PWM0 generator
(PWM0 and PWM0) are directed to all four sets of PWM output pairs. Setting
TMR3_PWM_CTL1[MM_EN] to 1 enables PWM Master mode. Assuming the outputs
are all enabled and no AND/OR gating is used, all four PWM output pairs transition
simultaneously under the direction of PWM0 and PWM0. In PWM Master mode,
the outputs still be gated individually using the AND/OR gating functions described in the
next section. Multi-PWM mode and the individual PWM outputs must be enabled along
with PWM Master mode. It is possible to enable or disable any combination of the 4 PWM
outputs while running in PWM Master mode.
Special circuitry is included for the update of the PWM edge transition values. Normal use
requires that these values be updated while the PWM generator is running.
Under certain circumstances, electric motors driven by the PWM logic encounters rough
operation. In other words, cycles are skipped if the PWM waveform edge is not carefully
modified.
Without special consideration, if a PWM generator looks for a particular count to make a
state transition and if the edge transition value changes to a value that already occurred in
Parameter
Timer Reload Value
PWM0 rising edge
PWM0 falling edge
PWM1 rising edge
PWM1 falling edge
PWM enable
PWM0 enable
PWM1 enable
Multi-PWM enable
Prescaler Divider = 4
PWM nonoverlapping delay = 0 TMR3_PWM_CTL2[PWM_DLY]
Control Register(s)
{TMR3_RR_H, TMR3_RR_L}
{TMR3_PWM0R_H,
TMR3_PWM0R_L}
{TMR3_PWM0F_H, TMR3_PWM0F_L} 0004h
{TMR3_PWM1R_H,
TMR3_PWM1R_L}
{TMR3_PWM1F_H, TMR3_PWM1F_L} 0007h
TMR3_PWM_CTL1[PAIR_EN]
TMR3_PWM_CTL1[PWM0_EN]
TMR3_PWM_CTL1[PWM1_EN]
TMR3_PWM_CTL1[MPWM_EN]
TMR3_CTL[CLK_DIV]
Programmable Reload Timers
Product Specification
eZ80F91 ASSP
Value
000Ch
0008h
0006h
1
1
1
1
00b
0000b
148
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