EZ80F91AZA50EG Zilog, EZ80F91AZA50EG Datasheet - Page 150

IC ACCLAIM MCU 256KB 144LQFP

EZ80F91AZA50EG

Manufacturer Part Number
EZ80F91AZA50EG
Description
IC ACCLAIM MCU 256KB 144LQFP
Manufacturer
Zilog
Series
eZ80® AcclaimPlus!™r
Datasheet

Specifications of EZ80F91AZA50EG

Core Processor
Z8
Core Size
8-Bit
Speed
50MHz
Connectivity
Ethernet, I²C, IrDA, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
32
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Oscillator Type
Internal
Operating Temperature
-40°C ~ 105°C
Package / Case
144-LQFP
Processor Series
EZ80F91x
Core
eZ80
Data Bus Width
8 bit
Data Ram Size
16 KB
Interface Type
I2C, IrDA, SPI
Maximum Clock Frequency
50 MHz
Number Of Programmable I/os
32
Number Of Timers
4
Operating Supply Voltage
3 V to 3.6 V
Maximum Operating Temperature
+ 105 C
Mounting Style
SMD/SMT
Development Tools By Supplier
eZ80F910300ZCOG
Minimum Operating Temperature
- 40 C
For Use With
269-4712 - KIT DEV ENCORE 32 SERIES269-4671 - BOARD ZDOTS SBC Z80ACCLAIM PLUS269-4561 - KIT DEV FOR EZ80F91 W/C-COMPILER269-4560 - KIT DEV FOR EZ80F91 W/C-COMPILER
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Data Converters
-
Lead Free Status / Rohs Status
 Details
Other names
269-4563

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
EZ80F91AZA50EG
Manufacturer:
Zilog
Quantity:
10 000
PS027001-0707
Timer Input Capture Value B Register—High Byte
The Timer x Input Capture Value B Register—High Byte (see
byte of the capture value for external input B. For Timer 1, the external input is IC0. For
Timer 3, it is IC3.
Table 65. Timer Input Capture Value Register B—High Byte
= 006Eh, TMR3_CAPB_H = 007Fh)
Timer Output Compare Control Register 1
The Timer3 Output Compare Control Register 1 (see
Mode and to provide initial values for the OC pins.
Table 66. Timer Output Compare Control Register 1
Bit
Reset
CPU Access
Note: R = Read only.
Bit
Position
[7:0]
TMR
Bit
Reset
CPU Access
Note: R = Read only; R/W = Read/Write.
Bit
Position
[7:6]
5
OC3_INIT
4
OC2_INIT
x
_CAPB_H
Value
00h–FFh
Value
00
0
1
0
1
R/W
R
7
0
7
0
Description
These bits represent the High byte of the 2-byte capture
value, {TMR
bit 15 (msb) of the 16-bit data value. Bit 0 is bit 8 of the 16-
bit timer data value.
Description
Unused
OC pin cleared when initialized.
OC pin set when initialized.
OC pin cleared when initialized.
OC pin set when initialized.
R/W
R
6
0
6
0
x
R/W
_CAPB_H[7:0], TMR
R
5
0
5
0
R/W
R
4
0
4
0
Table
66) is used to select the Master
R/W
R
3
0
3
0
(TMR3_OC_CTL1 = 0080h)
Table
Programmable Reload Timers
Product Specification
x
_CAPB_L[7:0]}. Bit 7 is
R/W
65) stores the High
R
2
0
2
0
(TMR1_CAPB_H
eZ80F91 ASSP
R/W
R
1
0
1
0
R/W
R
0
0
0
0
142

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