EZ80F91AZA50EG Zilog, EZ80F91AZA50EG Datasheet - Page 38

• Manufacturer Part Number: EZ80F91AZA50EG
• Description: IC ACCLAIM MCU 256KB 144LQFP
• Manufacturer: Zilog
• Series: eZ80® AcclaimPlus!™r

Specifications of EZ80F91AZA50EG

• Core Processor: Z8
• Core Size: 8-Bit
• Speed: 50MHz
• Connectivity: Ethernet, I²C, IrDA, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 144-LQFP
• Processor Series: EZ80F91x
• Core: eZ80
• Data Bus Width: 8 bit
• Data Ram Size: 16 KB
• Interface Type: I2C, IrDA, SPI
• Maximum Clock Frequency: 50 MHz
• Number Of Programmable I/os: 32
• Number Of Timers: 4
• Operating Supply Voltage: 3 V to 3.6 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: eZ80F910300ZCOG
• Minimum Operating Temperature: - 40 C
• For Use With: 269-4712 - KIT DEV ENCORE 32 SERIES269-4671 - BOARD ZDOTS SBC Z80ACCLAIM PLUS269-4561 - KIT DEV FOR EZ80F91 W/C-COMPILER269-4560 - KIT DEV FOR EZ80F91 W/C-COMPILER
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details
• Other names: 269-4563

Table 3. Register Map (Continued)
PS027001-0707
Address
(hex)
Ethernet Media Access Controller, continued
0053
0054
0055
0056
0057
0058
0059
PLL
005C
005D
005E
005F
Timers and PWM
0060
0061
0062
0063
0064
0065
0066
0067
0068
Mnemonic
EMAC_TRP_L
EMAC_TRP_H
EMAC_BLKSLFT_L
EMAC_BLKSLFT_H
EMAC_FDATA_L
EMAC_FDATA_H
EMAC_FFLAGS
PLL_DIV_L
PLL_DIV_H
PLL_CTL0
PLL_CTL1
TMR0_CTL
TMR0_IER
TMR0_IIR
TMR0_DR_L
TMR0_RR_L
TMR0_DR_H
TMR0_RR_H
TMR1_CTL
TMR1_IER
TMR1_IIR
TMR1_DR_L
TMR1_RR_L
Name
EMAC Transmit Read
Pointer—Low Byte
EMAC Transmit Read
Pointer—High Byte
EMAC Receive Blocks Left
Register—Low Byte
EMAC Receive Blocks Left
Register—High Byte
EMAC FIFO Data—Low Byte
EMAC FIFO Data—High Byte
EMAC FIFO Flags Register
PLL Divider Register—Low Byte
PLL Divider Register—High Byte
PLL Control Register 0
PLL Control Register 1
Timer 0 Control Register
Timer 0 Interrupt Enable Register
Timer 0 Interrupt Identification Register
Timer 0 Data Register—Low Byte
Timer 0 Reload Register—Low Byte
Timer 0 Data Register—High Byte
Timer 0 Reload Register—High Byte
Timer 1 Control Register
Timer 1 Interrupt Enable Register
Timer 1 Interrupt Identification Register
Timer 1 Data Register—Low Byte
Timer 1 Reload Register—Low Byte
Reset
(hex)
XX
XX
XX
XX
XX
XX
XX
0X
00
00
20
00
33
00
00
00
00
00
00
00
00
00
00
Product Specification
Access
eZ80F91 ASSP
CPU
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
W
W
W
W
W
R
R
R
Register Map
Page
333
334
334
335
336
336
337
272
273
273
275
132
133
135
136
138
137
139
132
133
135
136
138
No
30