EZ80F91AZA50EG Zilog, EZ80F91AZA50EG Datasheet - Page 157

• Manufacturer Part Number: EZ80F91AZA50EG
• Description: IC ACCLAIM MCU 256KB 144LQFP
• Manufacturer: Zilog
• Series: eZ80® AcclaimPlus!™r

Specifications of EZ80F91AZA50EG

• Core Processor: Z8
• Core Size: 8-Bit
• Speed: 50MHz
• Connectivity: Ethernet, I²C, IrDA, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 144-LQFP
• Processor Series: EZ80F91x
• Core: eZ80
• Data Bus Width: 8 bit
• Data Ram Size: 16 KB
• Interface Type: I2C, IrDA, SPI
• Maximum Clock Frequency: 50 MHz
• Number Of Programmable I/os: 32
• Number Of Timers: 4
• Operating Supply Voltage: 3 V to 3.6 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: eZ80F910300ZCOG
• Minimum Operating Temperature: - 40 C
• For Use With: 269-4712 - KIT DEV ENCORE 32 SERIES269-4671 - BOARD ZDOTS SBC Z80ACCLAIM PLUS269-4561 - KIT DEV FOR EZ80F91 W/C-COMPILER269-4560 - KIT DEV FOR EZ80F91 W/C-COMPILER
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details
• Other names: 269-4563

PS027001-0707
AND/OR Gating of the PWM Outputs
the current counter count-down cycle, then the transition is missed. The PWM generator
holds the current output state until the counter reloads and cycles through to the
appropriate edge transition value again. In effect, an entire cycle of the PWM waveform is
skipped with the signal held at a DC value. The change in PWM waveform duty cycle
from cycle to cycle must be limited to some fraction of a period to avoid rough running.
To avoid unintentional roughness due to timing of the load operation for the register val-
ues in question, the PWM edge transition values are double-buffered and exhibit the
following behavior:
•
•
When in Multi-PWM mode, it is possible for you to turn off PWM propagation to the pins
without disabling the PWM generator. This feature is global and applies to all enabled
PWM generators. The function is implemented by applying digital logic (AND or OR
functions) to combine the corresponding bits in the port output register with the PWM and
PWM outputs.
The AND or OR functions are enabled on all PWM outputs by setting
TMR3_PWM_CTL2[AO_EN] to either a 01b (AND) or 10b (OR). Any other value
disables this feature. Likewise, the AND or OR functions are enabled on all PWM outputs
by setting TMR3_PWM_CTL2[AON_EN] to either a 01b (AND) or 10b (OR). Any
other value disables this feature. A functional block diagram for the AND/OR gating fea-
ture for PWM0 and PWM0 is illustrated in
the other three PWM pairs are identical.
When the PWM generators are disabled, PWM edge transition values written by the
CPU are immediately loaded into the PWM edge transition registers.
When the PWM generators are enabled, a PWM edge transition value is loaded into a
buffer register and transferred to its destination register only during a specific transition
event. A rising edge transition value is only loaded upon a falling edge transition event,
and a falling edge transition value is only loaded upon a rising edge transition event.
Figure 33
on page 150. The functionality for
Programmable Reload Timers
Product Specification
eZ80F91 ASSP
149