EZ80F91AZA50EG Zilog, EZ80F91AZA50EG Datasheet - Page 17

• Manufacturer Part Number: EZ80F91AZA50EG
• Description: IC ACCLAIM MCU 256KB 144LQFP
• Manufacturer: Zilog
• Series: eZ80® AcclaimPlus!™r

Specifications of EZ80F91AZA50EG

• Core Processor: Z8
• Core Size: 8-Bit
• Speed: 50MHz
• Connectivity: Ethernet, I²C, IrDA, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 144-LQFP
• Processor Series: EZ80F91x
• Core: eZ80
• Data Bus Width: 8 bit
• Data Ram Size: 16 KB
• Interface Type: I2C, IrDA, SPI
• Maximum Clock Frequency: 50 MHz
• Number Of Programmable I/os: 32
• Number Of Timers: 4
• Operating Supply Voltage: 3 V to 3.6 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: eZ80F910300ZCOG
• Minimum Operating Temperature: - 40 C
• For Use With: 269-4712 - KIT DEV ENCORE 32 SERIES269-4671 - BOARD ZDOTS SBC Z80ACCLAIM PLUS269-4561 - KIT DEV FOR EZ80F91 W/C-COMPILER269-4560 - KIT DEV FOR EZ80F91 W/C-COMPILER
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details
• Other names: 269-4563

PS027001-0707
Table 2. Pin Identification on the eZ80F91 Device (Continued)
LQFP
Pin No
53
54
55
56
57
58
59
60
BGA
Pin No Symbol
M6
L6
K6
J6
M7
L7
K7
H6
INSTRD
WAIT
RESET
NMI
BUSREQ
BUSACK
V
V
DD
SS
Function
Reset
Instruction
Read Indicator
WAIT Request Schmitt-trigger
Nonmaskable
Interrupt
Bus Request
Bus
Acknowledge
Power Supply
Ground
Signal Direction Description
Output, Active
Low
input, Active Low
Bidirectional,
Active Low
Schmitt-trigger
input or open
drain output
Schmitt-trigger
input, Active Low,
edge-triggered
interrupt
Schmitt-trigger
input, Active Low
Output, Active
Low
INSTRD (with MREQ and RD)
indicates the eZ80F91 device is
fetching an instruction from memory.
This pin is in a high-impedance state
during bus acknowledge cycles.
Driving the WAIT pin Low forces the
CPU to wait additional clock cycles
for an external peripheral or external
memory to complete its Read or
Write operation.
This signal is used to initialize the
eZ80F91, and/or allow the ez80F91
to signal when it resets. See reset
section for the timing details. This
Schmitt-trigger input allows for RC
rise times.
The NMI input is a higher priority
input than the maskable interrupts. It
is always recognized at the end of
an instruction, regardless of the
state of the interrupt enable control
bits. This input includes a Schmitt-
trigger to allow for RC rise times.
External devices request the
eZ80F91 device to release the
memory interface bus for their use
by driving this pin Low.
The eZ80F91 device responds to a
Low on BUSREQ making the
address, data, and control signals
high impedance, and by driving the
BUSACK line Low. During bus
acknowledge cycles ADDR[23:0],
IORQ, and MREQ are inputs.
Power Supply.
Ground.
Product Specification
Architectural Overview
eZ80F91 ASSP
9