EZ80F91AZA50EG Zilog, EZ80F91AZA50EG Datasheet - Page 282

• Manufacturer Part Number: EZ80F91AZA50EG
• Description: IC ACCLAIM MCU 256KB 144LQFP
• Manufacturer: Zilog
• Series: eZ80® AcclaimPlus!™r

Specifications of EZ80F91AZA50EG

• Core Processor: Z8
• Core Size: 8-Bit
• Speed: 50MHz
• Connectivity: Ethernet, I²C, IrDA, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 144-LQFP
• Processor Series: EZ80F91x
• Core: eZ80
• Data Bus Width: 8 bit
• Data Ram Size: 16 KB
• Interface Type: I2C, IrDA, SPI
• Maximum Clock Frequency: 50 MHz
• Number Of Programmable I/os: 32
• Number Of Timers: 4
• Operating Supply Voltage: 3 V to 3.6 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: eZ80F910300ZCOG
• Minimum Operating Temperature: - 40 C
• For Use With: 269-4712 - KIT DEV ENCORE 32 SERIES269-4671 - BOARD ZDOTS SBC Z80ACCLAIM PLUS269-4561 - KIT DEV FOR EZ80F91 W/C-COMPILER269-4560 - KIT DEV FOR EZ80F91 W/C-COMPILER
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details
• Other names: 269-4563

PS027001-0707
Bit
Position
[5:4]
[3:2]
LDS_CTL1
[1:0]
CLK_MUX
Notes
1. Bits are programmed only when the PLL is disabled. The PLL is disabled when PLL_CTL1 bit
2. PLL cannot be selected when disabled or out of lock.
0 is equal to 0.
PLL Control Register 1
The PLL is enabled using this register. PLL lock-detect status, the PLL interrupt signals
and the PLL interrupt enables are accessed via this register. A brief description of each of
these PLL Control Register 1 attributes is listed below, and further described in
on page 275.
Lock Status (LCK_STATUS)—
read via this bit.
Interrupt Lock (INT_LOCK)—
module and indicates that a rising edge on the lock signal out of the PLL has been
observed.
Interrupt Unlock (INT_UNLOCK)—
module and indicates that a falling edge on the lock signal out of the PLL has been
observed.
Interrupt Lock Enable (INT_LOCK_EN)—
Interrupt Unlock Enable (INT_UNLOCK_EN)—
bit.
PLL Enable (PLL_ENABLE)—
Value Description
00
00
01
10
11
00
01
10
11
Reserved
Lock criteria—8 consecutive cycles of 20 ns
Lock criteria—16 consecutive cycles of 20 ns
Lock criteria—8 consecutive cycles of 400 ns
Lock criteria—16 consecutive cycles of 400 ns
System clock source is the external crystal oscillator
System clock source is the PLL
System clock source is the Real-Time Clock crystal oscillator
Reserved (previous select is preserved)
This signal feeds the interrupt line out of the CLKGEN
Enables/disables the PLL.
The current lock bit out of the PLL is synchronized and
This signal feeds the interrupt line out of the clkgen
2
This signal enables the interrupt lock bit.
This signal enables the interrupt unlock
Product Specification
Phase-Locked Loop
eZ80F91 ASSP
Table 155
274