EZ80F91AZA50EG Zilog, EZ80F91AZA50EG Datasheet - Page 339

• Manufacturer Part Number: EZ80F91AZA50EG
• Description: IC ACCLAIM MCU 256KB 144LQFP
• Manufacturer: Zilog
• Series: eZ80® AcclaimPlus!™r

Specifications of EZ80F91AZA50EG

• Core Processor: Z8
• Core Size: 8-Bit
• Speed: 50MHz
• Connectivity: Ethernet, I²C, IrDA, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 144-LQFP
• Processor Series: EZ80F91x
• Core: eZ80
• Data Bus Width: 8 bit
• Data Ram Size: 16 KB
• Interface Type: I2C, IrDA, SPI
• Maximum Clock Frequency: 50 MHz
• Number Of Programmable I/os: 32
• Number Of Timers: 4
• Operating Supply Voltage: 3 V to 3.6 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: eZ80F910300ZCOG
• Minimum Operating Temperature: - 40 C
• For Use With: 269-4712 - KIT DEV ENCORE 32 SERIES269-4671 - BOARD ZDOTS SBC Z80ACCLAIM PLUS269-4561 - KIT DEV FOR EZ80F91 W/C-COMPILER269-4560 - KIT DEV FOR EZ80F91 W/C-COMPILER
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details
• Other names: 269-4563

Table 218. EMAC PHY Read Status Data Register—High Byte
Table 219. EMAC MII Status Register
PS027001-0707
Bit
Reset
CPU Access
Note: R = Read Only.
Bit
Position
[7:0]
EMAC_PRSD_H
Bit
Reset
CPU Access
Note: R = Read Only.
Bit
Position
7
BUSY
6
MIILF
EMAC MII Status Register
The EMAC MII Status Register is used to determine the current state of the external PHY
device. See
Value
1
0
1
0
Value
00h–FFh These bits represent the High byte of the 2-byte EMAC
Description
MII management operation in progress—Busy. This status bit
goes busy whenever the LCTLD (PHY Write) or the RSTAT
(PHY Read) is set in the EMAC_MIIMGT register. It is
negated when the Write or Read operation to the PHY has
completed. In SCAN mode, the BUSY will be asserted until
the SCAN is disabled. Use the EmacIStat[MGTDONE]
interrupt status bit to determine when the data is valid.
Not Busy.
Local copy of PHY Link fail bit.
PHY Link OK.
R
R
7
0
7
0
Table
Description
PHY Read Status Data value, {EMAC_PRSD_H,
EMAC_PRSD_L}. Bit 7 is bit 15 (msb) of the 16-bit value.
Bit 0 is bit 8 of the 16-bit value.
219.
R
R
6
0
6
0
(EMAC_MIISTAT = 0050h)
R
R
5
0
5
0
R
R
4
0
4
0
R
R
3
0
3
0
R
R
2
0
2
0
(EMAC_PRSD_H = 004Fh)
Ethernet Media Access Controller
R
R
1
0
1
0
Product Specification
R
R
0
0
0
0
eZ80F91 ASSP
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