EZ80F91AZA50EG Zilog, EZ80F91AZA50EG Datasheet - Page 238
EZ80F91AZA50EG
Manufacturer Part Number
EZ80F91AZA50EG
Description
IC ACCLAIM MCU 256KB 144LQFP
Manufacturer
Zilog
Series
eZ80® AcclaimPlus!™r
Datasheet
1.EZ80F91AZA50SG.pdf
(387 pages)
Specifications of EZ80F91AZA50EG
Core Processor
Z8
Core Size
8-Bit
Speed
50MHz
Connectivity
Ethernet, I²C, IrDA, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
32
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Oscillator Type
Internal
Operating Temperature
-40°C ~ 105°C
Package / Case
144-LQFP
Processor Series
EZ80F91x
Core
eZ80
Data Bus Width
8 bit
Data Ram Size
16 KB
Interface Type
I2C, IrDA, SPI
Maximum Clock Frequency
50 MHz
Number Of Programmable I/os
32
Number Of Timers
4
Operating Supply Voltage
3 V to 3.6 V
Maximum Operating Temperature
+ 105 C
Mounting Style
SMD/SMT
Development Tools By Supplier
eZ80F910300ZCOG
Minimum Operating Temperature
- 40 C
For Use With
269-4712 - KIT DEV ENCORE 32 SERIES269-4671 - BOARD ZDOTS SBC Z80ACCLAIM PLUS269-4561 - KIT DEV FOR EZ80F91 W/C-COMPILER269-4560 - KIT DEV FOR EZ80F91 W/C-COMPILER
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Data Converters
-
Lead Free Status / Rohs Status
Details
Other names
269-4563
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
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Table 128. I
Table 129. I
PS027001-0707
Bit
Reset
CPU Access
Note: R = Read only.
Bit
Position
[7:3]
STAT
[2:0]
Code
00h
08h
10h
18h
20h
28h
30h
38h
Status
Bus error.
START condition transmitted.
Repeated START condition transmitted.
Address and Write bit transmitted, ACK received.
Address and Write bit transmitted, ACK not received.
Data byte transmitted in MASTER mode, ACK received.
Data byte transmitted in MASTER mode, ACK not received.
Arbitration lost in address or data byte.
2
2
C Status Registers
C Status Codes
I
The I
most-significant bits; the three least-significant bits are always 0. The Read Only
I2C_SR registers share the same I/O addresses as the Write Only I2C_CCR registers.
See
There are 29 possible status codes, as listed in
contains the status code
generated, and the IFLG bit in the I
correspond to a defined state of the I
When each of these states is entered, the corresponding status code appears in this register
and the IFLG bit in the I
tus code returns to
2
C Status Register
Value
00000–
11111
000
Table
2
C_SR register is a Read Only register that contains a 5-bit status code in the five
128.
R
7
1
Description
5-bit I
Reserved.
F8h
R
6
1
2
(I2C_SR = 00CCh)
C status code.
.
F8h
2
C_CTL register is set to 1. When the IFLG bit is cleared, the sta-
R
5
1
, no relevant status information is available, no interrupt is
2
R
4
1
C_CTL register is not set. All other status codes
2
C.
R
3
1
Table
R
2
0
129. When the I
R
1
0
Product Specification
R
2
0
0
I
C_SR register
2
C Serial I/O Interface
eZ80F91 ASSP
230
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