EZ80F91AZA50EG Zilog, EZ80F91AZA50EG Datasheet - Page 16

• Manufacturer Part Number: EZ80F91AZA50EG
• Description: IC ACCLAIM MCU 256KB 144LQFP
• Manufacturer: Zilog
• Series: eZ80® AcclaimPlus!™r

Specifications of EZ80F91AZA50EG

• Core Processor: Z8
• Core Size: 8-Bit
• Speed: 50MHz
• Connectivity: Ethernet, I²C, IrDA, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 144-LQFP
• Processor Series: EZ80F91x
• Core: eZ80
• Data Bus Width: 8 bit
• Data Ram Size: 16 KB
• Interface Type: I2C, IrDA, SPI
• Maximum Clock Frequency: 50 MHz
• Number Of Programmable I/os: 32
• Number Of Timers: 4
• Operating Supply Voltage: 3 V to 3.6 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: eZ80F910300ZCOG
• Minimum Operating Temperature: - 40 C
• For Use With: 269-4712 - KIT DEV ENCORE 32 SERIES269-4671 - BOARD ZDOTS SBC Z80ACCLAIM PLUS269-4561 - KIT DEV FOR EZ80F91 W/C-COMPILER269-4560 - KIT DEV FOR EZ80F91 W/C-COMPILER
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details
• Other names: 269-4563

PS027001-0707
Table 2. Pin Identification on the eZ80F91 Device (Continued)
LQFP
Pin No
39
40
41
42
43
44
45
46
47
48
49
50
51
52
BGA
Pin No Symbol
L2
K3
J4
M3
L3
H5
L4
M4
K4
G6
M5
L5
K5
J5
DATA0
DATA1
DATA2
DATA3
DATA4
DATA5
DATA6
DATA7
V
V
IORQ
MREQ
RD
WR
DD
SS
Function
Data Bus
Data Bus
Data Bus
Data Bus
Data Bus
Data Bus
Data Bus
Data Bus
Power Supply
Ground
Input/Output
Request
Memory
Request
Read
Write
Signal Direction Description
Bidirectional
Bidirectional
Bidirectional
Bidirectional
Bidirectional
Bidirectional
Bidirectional
Bidirectional
Bidirectional,
Active Low
Bidirectional,
Active Low
Output,
Active Low
Output, Active
Low
The data bus transfers data to and
from I/O and memory devices. The
eZ80F91 drives these lines only
during Write cycles when the
eZ80F91 is the bus master.
Power Supply.
Ground.
IORQ indicates that the CPU is
accessing a location in I/O space.
RD and WR indicate the type of
access. The eZ80F91 device does
not drive this line during RESET. It is
an input during bus acknowledge
cycles.
MREQ Low indicates that the CPU
is accessing a location in memory.
The RD, WR, and INSTRD signals
indicate the type of access. The
eZ80F91 device does not drive this
line during RESET. It is an input
during bus acknowledge cycles.
RD Low indicates that the eZ80F91
device is reading from the current
address location. This pin is in a
high-impedance state during bus
acknowledge cycles.
WR indicates that the CPU is writing
to the current address location. This
pin is in a high-impedance state
during bus acknowledge cycles.
Product Specification
Architectural Overview
eZ80F91 ASSP
8