EZ80F91AZA50EG Zilog, EZ80F91AZA50EG Datasheet - Page 95

• Manufacturer Part Number: EZ80F91AZA50EG
• Description: IC ACCLAIM MCU 256KB 144LQFP
• Manufacturer: Zilog
• Series: eZ80® AcclaimPlus!™r

Specifications of EZ80F91AZA50EG

• Core Processor: Z8
• Core Size: 8-Bit
• Speed: 50MHz
• Connectivity: Ethernet, I²C, IrDA, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 144-LQFP
• Processor Series: EZ80F91x
• Core: eZ80
• Data Bus Width: 8 bit
• Data Ram Size: 16 KB
• Interface Type: I2C, IrDA, SPI
• Maximum Clock Frequency: 50 MHz
• Number Of Programmable I/os: 32
• Number Of Timers: 4
• Operating Supply Voltage: 3 V to 3.6 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: eZ80F910300ZCOG
• Minimum Operating Temperature: - 40 C
• For Use With: 269-4712 - KIT DEV ENCORE 32 SERIES269-4671 - BOARD ZDOTS SBC Z80ACCLAIM PLUS269-4561 - KIT DEV FOR EZ80F91 W/C-COMPILER269-4560 - KIT DEV FOR EZ80F91 W/C-COMPILER
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details
• Other names: 269-4563

Table 29. Chip Select x Control Register (CS0_CTL = 00AAh, CS1_CTL = 00ADh,
CS2_CTL = 00B0h, CS3_CTL = 00B3h)
PS027001-0707
Bit
CS0_CTL Reset
CS1_CTL Reset
CS2_CTL Reset
CS3_CTL Reset
CPU Access
Note: R/W = Read/Write; R = Read Only.
Bit
Position
[7:5]
CSX_WAIT
4
CSX_IO
3
CSX_EN
[2:0]
Chip Select x Control Register
The Chip Select x Control register (see
type of chip select, and sets the number of wait states. The reset state for the Chip Select 0
Control register is
00h
Value Description
000
001
010
011
100
101
110
111
0
1
0
1
000
.
R/W
0 wait states are asserted when this chip select is active.
1 wait state is asserted when this chip select is active.
2 wait states are asserted when this chip select is active.
3 wait states are asserted when this chip select is active.
4 wait states are asserted when this chip select is active.
5 wait states are asserted when this chip select is active.
6 wait states are asserted when this chip select is active.
7 wait states are asserted when this chip select is active.
Chip select is configured as a memory chip select.
Chip select is configured as an I/O chip select.
Chip select is disabled.
Chip select is enabled.
Reserved.
7
1
0
0
0
R/W
E8h
6
1
0
0
0
when the reset state for the 3 other Chip Select Control registers is
R/W
5
1
0
0
0
R/W
4
0
0
0
0
Table
R/W
3
1
0
0
0
29) enables the chip selects, specifies the
R
2
0
0
0
0
R
1
0
0
0
0
Chip Selects and Wait States
Product Specification
R
0
0
0
0
0
eZ80F91 ASSP
87