EZ80F91AZA50EG Zilog, EZ80F91AZA50EG Datasheet - Page 186

• Manufacturer Part Number: EZ80F91AZA50EG
• Description: IC ACCLAIM MCU 256KB 144LQFP
• Manufacturer: Zilog
• Series: eZ80® AcclaimPlus!™r

Specifications of EZ80F91AZA50EG

• Core Processor: Z8
• Core Size: 8-Bit
• Speed: 50MHz
• Connectivity: Ethernet, I²C, IrDA, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 144-LQFP
• Processor Series: EZ80F91x
• Core: eZ80
• Data Bus Width: 8 bit
• Data Ram Size: 16 KB
• Interface Type: I2C, IrDA, SPI
• Maximum Clock Frequency: 50 MHz
• Number Of Programmable I/os: 32
• Number Of Timers: 4
• Operating Supply Voltage: 3 V to 3.6 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: eZ80F910300ZCOG
• Minimum Operating Temperature: - 40 C
• For Use With: 269-4712 - KIT DEV ENCORE 32 SERIES269-4671 - BOARD ZDOTS SBC Z80ACCLAIM PLUS269-4561 - KIT DEV FOR EZ80F91 W/C-COMPILER269-4560 - KIT DEV FOR EZ80F91 W/C-COMPILER
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details
• Other names: 269-4563

PS027001-0707
Note:
UART Interrupts
There are six different sources of interrupts from the UART. The six sources of interrupts
are:
•
•
•
UART Transmitter Interrupt
A Transmitter Hold Register Empty interrupt is generated if there is no data available in
the hold register. By the same token, a transmission complete interrupt is generated after
the data in the shift register is sent. Both interrupts are disabled using individual interrupt
enable bits, or cleared by writing data into the UARTx_THR register.
UART Receiver Interrupts
A receiver interrupt is generated by three possible events. The first event, a receiver data
ready interrupt event, indicates that one or more data bytes are received and are ready to
be read. Next, this interrupt is generated if the number of bytes in the receiver FIFO is
greater than or equal to the trigger level. If the FIFO is not enabled, the interrupt is gener-
ated if the receive buffer contains a data byte. This interrupt is cleared by reading the
UARTx_RBR.
The second interrupt source is the receiver time-out. A receiver time-out interrupt is gen-
erated when there are fewer data bytes in the receiver FIFO than the trigger level and there
are no Reads and Writes to or from the receiver FIFO for four consecutive byte times.
When the receiver time-out interrupt is generated, it is cleared only after emptying the
entire receive FIFO.
The first two interrupt sources from the receiver (data ready and time-out) share an inter-
rupt enable bit. The third source of a receiver interrupt is a line status error, indicating an
error in byte reception. This error results from:
•
For 9-bit data, incorrect parity indicates detection of an address byte.
•
•
•
Transmitter (two different interrupts)
Receiver (three different interrupts)
Modem status
Incorrect received parity.
Incorrect framing (that is, the stop bit) is not detected by receiver at the end of the byte.
Receiver overrun condition.
A BREAK condition being detected on the receive data input.
Universal Asynchronous Receiver/Transmitter
Product Specification
eZ80F91 ASSP
178