EZ80F91AZA50EG Zilog, EZ80F91AZA50EG Datasheet - Page 375

• Manufacturer Part Number: EZ80F91AZA50EG
• Description: IC ACCLAIM MCU 256KB 144LQFP
• Manufacturer: Zilog
• Series: eZ80® AcclaimPlus!™r

Specifications of EZ80F91AZA50EG

• Core Processor: Z8
• Core Size: 8-Bit
• Speed: 50MHz
• Connectivity: Ethernet, I²C, IrDA, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 144-LQFP
• Processor Series: EZ80F91x
• Core: eZ80
• Data Bus Width: 8 bit
• Data Ram Size: 16 KB
• Interface Type: I2C, IrDA, SPI
• Maximum Clock Frequency: 50 MHz
• Number Of Programmable I/os: 32
• Number Of Timers: 4
• Operating Supply Voltage: 3 V to 3.6 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: eZ80F910300ZCOG
• Minimum Operating Temperature: - 40 C
• For Use With: 269-4712 - KIT DEV ENCORE 32 SERIES269-4671 - BOARD ZDOTS SBC Z80ACCLAIM PLUS269-4561 - KIT DEV FOR EZ80F91 W/C-COMPILER269-4560 - KIT DEV FOR EZ80F91 W/C-COMPILER
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details
• Other names: 269-4563

DATA4 8
DATA5 8
DATA6 8
DATA7 8
DC Characteristics 344
DCD 191, 194
DCD0 13, 200
DCD1 16
DCTS 194
DDCD 194
DDSR 194
Divider, PLL 270
divisor count 208
divisor count, 16-bit 182
DSR 192, 194
DSR0 13, 200
DSR1 16
DTACK 81, 82
DTR 192, 194
DTR0 12, 200
DTR1 15
E
EC0 17, 127, 129, 132
EC1 22, 127, 129, 132
edge-selectable interrupts 55
Edge-Triggered Interrupts 54
EI, Op Code Map 284
EMAC 291
EMAC Address Filter Register 315
EMAC Boundary Pointer Register—Low and High
Bytes 323
EMAC Boundary Pointer Register—Upper Byte
323
EMAC Buffer Size Register 326
EMAC Configuration Register 1 303
EMAC Configuration Register 2 305
EMAC Configuration Register 3 306
EMAC Configuration Register 4 307
EMAC FIFO Data Register—Low and High Bytes
336
EMAC FIFO Flags Register 337
EMAC Functional Description 292
PS027001-0707
EMAC Hash Table Register 316
EMAC Interpacket Gap 309
EMAC Interpacket Gap Overview 309
EMAC Interpacket Gap Register 311
EMAC Interrupt Enable Register 327
EMAC Interrupt Status Register 329
EMAC Interrupts 296
EMAC Maximum Frame Length Register—Low
and High Bytes 313
EMAC memory 292, 293
EMAC MII Management Register 317
EMAC MII Status Register 331
EMAC Non-Back-To-Back IPG Register—Part 1
312
EMAC Non-Back-To-Back IPG Register—Part 2
312
EMAC PHY Address Register 319
EMAC PHY Configuration Data Register—Low
Byte 318
EMAC PHY Read Status Data Register—Low and
High Bytes 330
EMAC PHY Unit Select Address Register 320
EMAC RAM 93, 94, 95, 96
EMAC Receive Blocks Left Register—Low and
High Bytes 334
EMAC Receive High Boundary Pointer Register—
Low and High Bytes 324
EMAC Receive Read Pointer Register—Low and
High Bytes 325
EMAC Receive Write Pointer Register—High Byte
333
EMAC Receive Write Pointer Register—Low Byte
332
EMAC Receiver Interrupts 296
EMAC Registers 301
EMAC Reset Control Register 321
EMAC Shared Memory Organization 296
EMAC Station Address Register 307
EMAC System Interrupts 296
EMAC Test Register 302
EMAC Transmit Lower Boundary Pointer Regis-
ter—Low and High Bytes 322
EMAC Transmit Pause Timer Value Register—
Low and High Bytes 309
Product Specification
eZ80F91 ASSP
367