EZ80F91AZA50EG Zilog, EZ80F91AZA50EG Datasheet - Page 232

• Manufacturer Part Number: EZ80F91AZA50EG
• Description: IC ACCLAIM MCU 256KB 144LQFP
• Manufacturer: Zilog
• Series: eZ80® AcclaimPlus!™r

Specifications of EZ80F91AZA50EG

• Core Processor: Z8
• Core Size: 8-Bit
• Speed: 50MHz
• Connectivity: Ethernet, I²C, IrDA, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 144-LQFP
• Processor Series: EZ80F91x
• Core: eZ80
• Data Bus Width: 8 bit
• Data Ram Size: 16 KB
• Interface Type: I2C, IrDA, SPI
• Maximum Clock Frequency: 50 MHz
• Number Of Programmable I/os: 32
• Number Of Timers: 4
• Operating Supply Voltage: 3 V to 3.6 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: eZ80F910300ZCOG
• Minimum Operating Temperature: - 40 C
• For Use With: 269-4712 - KIT DEV ENCORE 32 SERIES269-4671 - BOARD ZDOTS SBC Z80ACCLAIM PLUS269-4561 - KIT DEV FOR EZ80F91 W/C-COMPILER269-4560 - KIT DEV FOR EZ80F91 W/C-COMPILER
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details
• Other names: 269-4563

PS027001-0707
Note:
I
ing the transmission of an address, and the slave address and Read bit are received. This
action is represented by the status code
The data byte to be transmitted is loaded into the I
cleared to 0. After the I
and the I
the I
byte is transmitted, the IFLG is set and the I
returns to an idle state. The AAK bit must be set to 1 before reentering SLAVE mode.
If no ACK is received after transmitting a byte, the IFLG is set and the I
contains
If a STOP condition is detected after an ACK bit, the I
Slave Receive
In SLAVE RECEIVE mode, a number of data bytes are received from a master transmit-
ter.
The I
Write bit (lsb = 0) after a START condition. The I
IFLG bit in the I
The I
(if the GCE bit in the I
When the I
ister), it transmits an acknowledge after the first address byte is received but no interrupt is
generated. IFLG is not set and the status does not change. The I
only after the second address byte is received. The I
tus code as described above.
I
the transmission of an address, and the slave address and Write bit (or the general call
address if the CGE bit in the I
the I
address is received. The IFLG bit must be cleared to 0 to allow data transfer to continue.
If the AAK bit in the I
transmitted and the IFLG bit is set after each byte is received. The I
tains the two status codes
eral call address. The received data byte are read from the I
bit must be cleared to allow the transfer to continue. If a STOP condition or a repeated
START condition is detected after the acknowledge bit, the IFLG bit is set and the I
register contains status code
2
2
C goes from MASTER mode to SLAVE TRANSMIT mode when arbitration is lost dur-
C goes from MASTER mode to SLAVE RECEIVE mode when arbitration is lost during
2
2
2
2
C_SR register is
C_DR register, the AAK bit is cleared when the IFLG is cleared to 0. After the final
C also enters SLAVE RECEIVE mode when it receives the general call address
C enters SLAVE RECEIVE mode when it receives its own slave address and a
2
C0h
C_SR register contains
2
C contains a 10-bit slave address (signified by
. The I
2
C_CTL register and the I
2
C then returns to an idle state.
2
68h
2
2
C_CTL register is set to 1 then an ACK bit (Low level on SDA) is
C_SAR register is set). The status code is then
C transmits the byte and receives an ACK, the IFLG bit is set to 1
80h
if the slave address is received or
A0h
2
C_SAR register is set to 1) are received. The status code in
or
.
B8h
90h
. When the final byte to be transmitted is loaded into
if SLAVE RECEIVE mode is entered with the gen-
B0h
2
C_SR register contains the status code
2
in the I
C_SR register contains
2
2
C transmits an ACK bit and sets the
C_DR register and the IFLG bit is
2
2
C_SR register.
C sets the IFLG bit and loads the sta-
2
C returns to an idle state.
F0h–F7h
2
C_DR register and the IFLG
78h
2
Product Specification
C generates an interrupt
if the general call
2
C8h
C_SR register con-
in the I
I
2
70h
C Serial I/O Interface
2
eZ80F91 ASSP
C_SR register
and the I
.
2
C_SAR reg-
2
60h
2
C
C_SR
00h
.
224