EZ80F91AZA50EG Zilog, EZ80F91AZA50EG Datasheet - Page 302

• Manufacturer Part Number: EZ80F91AZA50EG
• Description: IC ACCLAIM MCU 256KB 144LQFP
• Manufacturer: Zilog
• Series: eZ80® AcclaimPlus!™r

Specifications of EZ80F91AZA50EG

• Core Processor: Z8
• Core Size: 8-Bit
• Speed: 50MHz
• Connectivity: Ethernet, I²C, IrDA, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 144-LQFP
• Processor Series: EZ80F91x
• Core: eZ80
• Data Bus Width: 8 bit
• Data Ram Size: 16 KB
• Interface Type: I2C, IrDA, SPI
• Maximum Clock Frequency: 50 MHz
• Number Of Programmable I/os: 32
• Number Of Timers: 4
• Operating Supply Voltage: 3 V to 3.6 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: eZ80F910300ZCOG
• Minimum Operating Temperature: - 40 C
• For Use With: 269-4712 - KIT DEV ENCORE 32 SERIES269-4671 - BOARD ZDOTS SBC Z80ACCLAIM PLUS269-4561 - KIT DEV FOR EZ80F91 W/C-COMPILER269-4560 - KIT DEV FOR EZ80F91 W/C-COMPILER
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details
• Other names: 269-4563

PS027001-0707
Table 174. Arbiter Priority
TxDMA
The TxDMA module moves the next packet to be transmitted from EMAC memory into
the TxFIFO. Whenever the polling timer expires, the TxDMA reads the High status byte
from the Tx descriptor table pointed to by the Transmit Read Pointer, TRP. Polling contin-
ues until the High status Read reaches bit 7, when the Emac_Owns ownership semaphore,
bit 15 of the descriptor table (see
tializes the packet length counter with the size of the packet from descriptor table bytes 3
and 4. The TxDMA moves the data into the TxFIFO until the packet length counter down-
counts to zero. The TxDMA then waits for Transmission Complete signal to be asserted to
indicate that the packet is sent and that the Transmit status from the EMAC is valid. The
TxDMA updates the descriptor table status and resets the ownership semaphore, bit 15.
Finally, the Tx_DONE_STAT bit of the EMAC Interrupt Status Register is set to 1, the
address field, DMA_Address, is updated from the descriptor table next pointer, NP (see
Figure 62
is ready to be transmitted.
While the TxDMA is filling the TxFIFO, it monitors two signals from the Transmit FIFO
State Machine (TxFifoSM) to detect error conditions and to determine if the packet is to
be retransmitted (TxDMA_Retry asserted) or the packet is aborted (TxDMA_Abort
asserted). If the packet is aborted, the TxDMA updates the descriptor status and moves to
the next packet. If the packet is to be retried, the DMA_Address is reset to the start of the
packet, the packet length counter is reloaded from the descriptor table, bytes 3 and 4, and
the packet is moved into the TxFIFO again. When an abort or retry event occurs, the
TxDMA asserts the appropriate signal to reset the TxFIFO Read and Write pointers which
clears out any data that is in the FIFO. The TxFifoSM negates the TxDMA_Abort or
TxDMA_Retry signal(s) or both when the TxFCWP signal is High. This handshaking
maintains synchronization between the TxDMA and the TxFifoSM.
RxDMA
The RxDMA reads the data from the RxFIFO and stores it in the EMAC memory Receive
buffer. When the end of the packet is detected, the RxDMA reads the next two bytes from
Priority
Level
0
1
2
3
4
on page 298). The High byte of the status is read to determine if the next packet
Device
Serviced
RxDMA High
TxDMA High
eZ80
RxDMA Low
TxDMA Low
®
CPU
Flags
RxFIFO > half full (FAF)
TxFIFO < half full (FAE)
RxFIFO < half full (FAE)
TxFIFO > half full (FAF)
Table 178
on page 299) is set to 1. The TxDMA then ini-
Ethernet Media Access Controller
Product Specification
eZ80F91 ASSP
294