EZ80F91AZA50EG Zilog, EZ80F91AZA50EG Datasheet - Page 317

• Manufacturer Part Number: EZ80F91AZA50EG
• Description: IC ACCLAIM MCU 256KB 144LQFP
• Manufacturer: Zilog
• Series: eZ80® AcclaimPlus!™r

Specifications of EZ80F91AZA50EG

• Core Processor: Z8
• Core Size: 8-Bit
• Speed: 50MHz
• Connectivity: Ethernet, I²C, IrDA, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 144-LQFP
• Processor Series: EZ80F91x
• Core: eZ80
• Data Bus Width: 8 bit
• Data Ram Size: 16 KB
• Interface Type: I2C, IrDA, SPI
• Maximum Clock Frequency: 50 MHz
• Number Of Programmable I/os: 32
• Number Of Timers: 4
• Operating Supply Voltage: 3 V to 3.6 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: eZ80F910300ZCOG
• Minimum Operating Temperature: - 40 C
• For Use With: 269-4712 - KIT DEV ENCORE 32 SERIES269-4671 - BOARD ZDOTS SBC Z80ACCLAIM PLUS269-4561 - KIT DEV FOR EZ80F91 W/C-COMPILER269-4560 - KIT DEV FOR EZ80F91 W/C-COMPILER
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details
• Other names: 269-4563

Table 187. EMAC Transmit Pause Timer Value Register—Low Byte
Table 188.
PS027001-0707
Bit
Reset
CPU Access
Note: R/W = Read/Write.
Bit
Position
[7:0]
EMAC_TPTV_L
Bit
Reset
CPU Access
Note: R/W = Read/Write.
Bit
Position
[7:0]
EMAC_TPTV_H
EMAC Interpacket Gap
EMAC Transmit Pause Timer Value
EMAC Transmit Pause Timer Value Register—Low and High Bytes
The Low and High bytes of the EMAC Transmit Pause Timer Value Register are inserted
into outgoing pause control frames. See
EMAC Interpacket Gap Overview
Interpacket Gap (IPG) is measured between the last nibble of the frame check sequence
(FCS) and the first nibble of the preamble of the next packet. Three registers are available
to fine tune the IPG, the EMAC_IPGT, EMAC_IPGR1, and the EMAC_IPGR2. The first
register EMAC_IPGT determines the back-to-back Transmit IPG. The other two registers
determine the non-back-to-back IPG in two parts.
for the EMAC_IPGT and the corresponding IPGs for both FULL-DUPLEX and HALF-
DUPLEX modes.
Value
00h–FFh The 16-bit value, {EMAC_TPTV_H, EMAC_TPTV_L}, is
Value
00h–FFh The 16-bit value, {EMAC_TPTV_H, EMAC_TPTV_L}, is
R/W
R/W
Description
inserted into outgoing pause control frames as the pause
timer value upon asserting TPCF.
Description
inserted into outgoing pause control frames as the pause
timer value upon asserting TPCF.
7
0
7
0
R/W
R/W
6
0
6
0
R/W
R/W
5
0
5
0
R/W
R/W
Register
4
0
4
0
Table 187
R/W
R/W
3
0
3
0
—High Byte
Table 189
and
R/W
R/W
2
0
2
0
Table 188
(EMAC_TPTV_L = 002Bh)
Ethernet Media Access Controller
R/W
R/W
on page 310 shows the values
1
0
1
0
(EMAC_TPTV_H = 002Ch)
Product Specification
on page 309.
R/W
R/W
0
0
0
0
eZ80F91 ASSP
309