EZ80F91AZA50EG Zilog, EZ80F91AZA50EG Datasheet - Page 241

• Manufacturer Part Number: EZ80F91AZA50EG
• Description: IC ACCLAIM MCU 256KB 144LQFP
• Manufacturer: Zilog
• Series: eZ80® AcclaimPlus!™r

Specifications of EZ80F91AZA50EG

• Core Processor: Z8
• Core Size: 8-Bit
• Speed: 50MHz
• Connectivity: Ethernet, I²C, IrDA, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 144-LQFP
• Processor Series: EZ80F91x
• Core: eZ80
• Data Bus Width: 8 bit
• Data Ram Size: 16 KB
• Interface Type: I2C, IrDA, SPI
• Maximum Clock Frequency: 50 MHz
• Number Of Programmable I/os: 32
• Number Of Timers: 4
• Operating Supply Voltage: 3 V to 3.6 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: eZ80F910300ZCOG
• Minimum Operating Temperature: - 40 C
• For Use With: 269-4712 - KIT DEV ENCORE 32 SERIES269-4671 - BOARD ZDOTS SBC Z80ACCLAIM PLUS269-4561 - KIT DEV FOR EZ80F91 W/C-COMPILER269-4560 - KIT DEV FOR EZ80F91 W/C-COMPILER
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details
• Other names: 269-4563

Table 131. I
PS027001-0707
Bit
Reset
CPU Access
Note: W = Write Only.
Bit
Position
[7:0]
SRR
2
C Software Reset Register
programmable clock divider stages, a high sampling frequency is ensured while allowing
the MASTER mode output to be set to a lower frequency.
Bus Clock Speed
The I
To ensure correct detection of START and STOP conditions on the bus, the I
ple the I
bus. The sampling frequency must therefore be at least 1 MHz (4 MHz in FAST mode) to
guarantee correct operation with other bus masters.
The I
and the value in the I
MASTER mode is determined by the frequency of the input clock and the values in
I
I
The I
a software reset of the I
2
2
C Software Reset Register
C_CCR[2:0] and I
Value
00h–FFh Writing any value to this register performs a software reset
2
2
2
C bus is defined for bus clock speeds up to 100 kbps (400 kbps in FAST mode).
C sampling frequency is determined by the frequency of the eZ80F91 system clock
C_SRR register is a Write Only register. Writing any value to this register performs
2
X
W
C bus at least ten times faster than the bus clock speed of the fastest master on the
7
Description
of the I
X
W
6
2
2
2
C_CCR[6:3].
C_CCR bits 2 to 0. The bus clock speed generated by the I
C module.
2
C module. See
X
W
5
(I2C_SRR = 00CDh)
X
W
4
Table
X
W
3
131.
X
W
2
X
W
1
Product Specification
X
W
0
I
2
C Serial I/O Interface
eZ80F91 ASSP
2
C must sam-
2
C in
233