EZ80F91AZA50EG Zilog, EZ80F91AZA50EG Datasheet - Page 230

• Manufacturer Part Number: EZ80F91AZA50EG
• Description: IC ACCLAIM MCU 256KB 144LQFP
• Manufacturer: Zilog
• Series: eZ80® AcclaimPlus!™r

Specifications of EZ80F91AZA50EG

• Core Processor: Z8
• Core Size: 8-Bit
• Speed: 50MHz
• Connectivity: Ethernet, I²C, IrDA, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 144-LQFP
• Processor Series: EZ80F91x
• Core: eZ80
• Data Bus Width: 8 bit
• Data Ram Size: 16 KB
• Interface Type: I2C, IrDA, SPI
• Maximum Clock Frequency: 50 MHz
• Number Of Programmable I/os: 32
• Number Of Timers: 4
• Operating Supply Voltage: 3 V to 3.6 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: eZ80F910300ZCOG
• Minimum Operating Temperature: - 40 C
• For Use With: 269-4712 - KIT DEV ENCORE 32 SERIES269-4671 - BOARD ZDOTS SBC Z80ACCLAIM PLUS269-4561 - KIT DEV FOR EZ80F91 W/C-COMPILER269-4560 - KIT DEV FOR EZ80F91 W/C-COMPILER
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details
• Other names: 269-4563

Table 121. I
PS027001-0707
Code
40h
48h
38h
68h
78h
B0h
Notes
1. AAK is an I 2 C control bit that identifies which ACK signal to transmit.
2. R is defined as the Read bit; that is, the lsb is set to 1.
3. W is defined as the Write bit; that is, the lsb is cleared to 0.
I
Addr + R transmitted,
ACK received
Addr + R transmitted,
ACK not received
Arbitration lost
Arbitration lost,
SLA+W received,
ACK transmitted
Arbitration lost,
General call addr
received, ACK
transmitted
Arbitration lost,
SLA+R received,
ACK transmitted
2
C State
2
C Master Receive Status Codes
If 10-bit addressing is being used, the slave is first addressed using the full 10-bit address,
plus the Write bit. The master then issues a restart followed by the first part of the 10-bit
3
2
ASSP Response
For a 7-bit address,
clear IFLG, AAK = 0
Or clear IFLG, AAK = 1
For a 10-bit address
Write extended address
byte to data, clear IFLG
For a 7-bit address:
Set STA, clear IFLG
Or set STP, clear IFLG
Or set STA & STP,
clear IFLG
For a 10-bit address:
Write extended address byte to
data, clear IFLG
Clear IFLG
Or set STA, clear IFLG
Clear IFLG, clear AAK = 0
Or clear IFLG, set AAK = 1
Same as code 68h
Write byte to DATA,
clear IFLG, clear AAK = 0
Or write byte to DATA,
clear IFLG, set AAK = 1
1
Next I
Same as code 68h
Receive data byte,
transmit NACK
Receive data byte,
transmit ACK
Transmit extended address byte
Transmit repeated START
Transmit STOP
Transmit STOP then START
Transmit extended address byte
Return to idle
Transmit START when bus is free
Receive data byte,
transmit NACK
Receive data byte,
transmit ACK
Transmit last byte,
receive ACK
Transmit data byte,
receive ACK
2
C Action
Product Specification
I
2
C Serial I/O Interface
eZ80F91 ASSP
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