EZ80F91AZA50EG Zilog, EZ80F91AZA50EG Datasheet - Page 197

• Manufacturer Part Number: EZ80F91AZA50EG
• Description: IC ACCLAIM MCU 256KB 144LQFP
• Manufacturer: Zilog
• Series: eZ80® AcclaimPlus!™r

Specifications of EZ80F91AZA50EG

• Core Processor: Z8
• Core Size: 8-Bit
• Speed: 50MHz
• Connectivity: Ethernet, I²C, IrDA, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 144-LQFP
• Processor Series: EZ80F91x
• Core: eZ80
• Data Bus Width: 8 bit
• Data Ram Size: 16 KB
• Interface Type: I2C, IrDA, SPI
• Maximum Clock Frequency: 50 MHz
• Number Of Programmable I/os: 32
• Number Of Timers: 4
• Operating Supply Voltage: 3 V to 3.6 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: eZ80F910300ZCOG
• Minimum Operating Temperature: - 40 C
• For Use With: 269-4712 - KIT DEV ENCORE 32 SERIES269-4671 - BOARD ZDOTS SBC Z80ACCLAIM PLUS269-4561 - KIT DEV FOR EZ80F91 W/C-COMPILER269-4560 - KIT DEV FOR EZ80F91 W/C-COMPILER
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details
• Other names: 269-4563

PS027001-0707
Bit
Position Value
4
EPS
3
PEN
[2:0]
CHAR
0
1
0
1
000–111
Table 103. UART Character Parameter Definition
Table 104. Parity Select Definition for Multidrop Communications
CHAR[2:0] Character Length (Tx/Rx Data Bits)
Multidrop Mode
Description
Even Parity Select
Use odd parity for transmit and receive. The total number of 1 bits in the transmit
data plus parity bit is odd. Used as SPACE bit in Multidrop Mode. See
page 189 for parity select definitions. Note: Receive Parity is set to SPACE in
multidrop mode.
Use even parity for transmit and receive. The total number of 1 bits in the transmit
data plus parity bit is even. Used as MARK bit in Multidrop Mode. See
page 189 for parity select definitions.
Parity bit transmit and receive is disabled.
Parity bit transmit and receive is enabled. For transmit, a parity bit is generated and
transmitted with every data character. For receive, the parity is checked for every
incoming data character. In Multidrop Mode, receive parity is checked for space
parity.
UART Character Parameter Selection
See
000
001
010
100
101
011
110
111
Table 103
0
0
on page 189 for a description of the values.
Even Parity Select
5
6
7
8
5
6
7
8
0
1
Universal Asynchronous Receiver/Transmitter
Stop Bits (Tx Stop Bits)
Parity Type
even
odd
Product Specification
1
1
1
1
2
2
2
2
eZ80F91 ASSP
Table 104
Table 104
on
on
189