EZ80F91AZA50EG Zilog, EZ80F91AZA50EG Datasheet - Page 298

• Manufacturer Part Number: EZ80F91AZA50EG
• Description: IC ACCLAIM MCU 256KB 144LQFP
• Manufacturer: Zilog
• Series: eZ80® AcclaimPlus!™r

Specifications of EZ80F91AZA50EG

• Core Processor: Z8
• Core Size: 8-Bit
• Speed: 50MHz
• Connectivity: Ethernet, I²C, IrDA, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 144-LQFP
• Processor Series: EZ80F91x
• Core: eZ80
• Data Bus Width: 8 bit
• Data Ram Size: 16 KB
• Interface Type: I2C, IrDA, SPI
• Maximum Clock Frequency: 50 MHz
• Number Of Programmable I/os: 32
• Number Of Timers: 4
• Operating Supply Voltage: 3 V to 3.6 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: eZ80F910300ZCOG
• Minimum Operating Temperature: - 40 C
• For Use With: 269-4712 - KIT DEV ENCORE 32 SERIES269-4671 - BOARD ZDOTS SBC Z80ACCLAIM PLUS269-4561 - KIT DEV FOR EZ80F91 W/C-COMPILER269-4560 - KIT DEV FOR EZ80F91 W/C-COMPILER
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details
• Other names: 269-4563

Table 173. Opcode Map—Fourth Byte After 0FDh, 0CBh, and dd
Legend
PS027001-0707
First Operand
of Fourth
A
B
C
D
E
0
1
2
3
4
5
6
7
8
9
F
Nibble
Upper
Note: d = 8-bit two’s-complement displacement
Byte
0
Lower Nibble of 4th Byte
4
1
0,(IY+d)
BIT
6
2
Second Operand
Mnemonic
3
4
5
RES 0,
RES 2,
RES 4,
RES 6,
SET 0,
SET 2,
SET 4,
SET 6,
(IY+d)
(IY+d)
(IY+d)
(IY+d)
(IY+d)
(IY+d)
(IY+d)
(IY+d)
(IY+d)
(IY+d)
(IY+d)
(IY+d)
(IY+d)
(IY+d)
(IY+d)
BIT 0,
BIT 2,
BIT 4,
BIT 6,
RLC
SLA
RL
6
Lower Nibble (Hex)
7
8
9
A
B
Product Specification
eZ80
C
®
CPU Instruction Set
eZ80F91 ASSP
D
RES 1,
RES 3,
RES 5,
RES 7,
SET 1,
SET 3,
SET 5,
SET 7,
(IY+d)
(IY+d)
(IY+d)
(IY+d)
(IY+d)
(IY+d)
(IY+d)
(IY+d)
(IY+d)
(IY+d)
(IY+d)
(IY+d)
(IY+d)
(IY+d)
(IY+d)
(IY+d)
BIT 1,
BIT 3,
BIT 5,
BIT 7,
RRC
SRA
SRL
RR
E
F
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