HD64F38024DV Renesas Electronics America, HD64F38024DV Datasheet - Page 113

• Manufacturer Part Number: HD64F38024DV
• Description: IC H8/SLP MCU FLASH 80QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300L SLPr

Specifications of HD64F38024DV

• Core Processor: H8/300L
• Core Size: 8-Bit
• Speed: 10MHz
• Connectivity: SCI
• Peripherals: LCD, PWM, WDT
• Number Of I /o: 51
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 3 Exception Handling
Interrupts IRQ
, IRQ
, IRQ
and IRQ
4
3
1
0
Interrupts IRQ4, IRQ3, IRQ1, and IRQ0 are requested by input signals to pins IRQ
, IRQ
, IRQ
,
4
3
1
and IRQ
. These interrupts are detected by either rising edge sensing or falling edge sensing,
0
depending on the settings of bits IEG4, IEG3, IEG1, and IEG0 in IEGR.
When these pins are designated as pins IRQ
, IRQ
, IRQ
, and IRQ
in port mode register B, 2,
4
3
1
0
and 1 and the designated edge is input, the corresponding bit in IRR1 is set to 1, requesting an
interrupt. Recognition of these interrupt requests can be disabled individually by clearing bits
IEN4, IEN3, IEN1, and IEN0 to 0 in IENR1. These interrupts can all be masked by setting the I
bit to 1 in CCR.
When IRQ4, IRQ3, IRQ1, and IRQ0 interrupt exception handling is initiated, the I bit is set to 1 in
CCR. Vector numbers 8, 7, 5, and 4 are assigned to interrupts IRQ4, IRQ3, IRQ1, and IRQ0. The
order of priority is from IRQ0 (high) to IRQ4 (low). Table 3.2 gives details.
IRQAEC Interrupt
The IRQAEC interrupt is requested by an input signal to pin IRQAEC and IECPWM (output of
PWM for AEC). When the IRQAEC input pin is to be used as an external interrupt, set ECPWME
in AEGSR to 0. This interrupt is detected by rising edge, falling edge, or both edge sensing,
depending on the settings of bits AIEGS1 and AIEGS0 in AEGSR.
When bit IENEC2 in IENR1 is 1 and the designated edge is input, the corresponding bit in IRR1 is
set to 1, requesting an interrupt.
When IRQAEC interrupt exception handling is initiated, the I bit is set to 1 in CCR. Vector
number 6 is assigned to the IRQAEC interrupt exception handling. Table 3.2 gives details.
3.3.4
Internal Interrupts
There are 9 internal interrupts that can be requested by the on-chip peripheral modules. When a
peripheral module requests an interrupt, the corresponding bit in IRR1 or IRR2 is set to 1.
Recognition of individual interrupt requests can be disabled by clearing the corresponding bit in
IENR1 or IENR2. All these interrupts can be masked by setting the I bit to 1 in CCR. When
internal interrupt handling is initiated, the I bit is set to 1 in CCR. Vector numbers from 20 to 18
and 16 to 11 are assigned to these interrupts. Table 3.2 shows the order of priority of interrupts
from on-chip peripheral modules.
Rev. 8.00 Mar. 09, 2010 Page 91 of 658
REJ09B0042-0800