HD64F38024DV Renesas Electronics America, HD64F38024DV Datasheet - Page 309

• Manufacturer Part Number: HD64F38024DV
• Description: IC H8/SLP MCU FLASH 80QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300L SLPr

Specifications of HD64F38024DV

• Core Processor: H8/300L
• Core Size: 8-Bit
• Speed: 10MHz
• Connectivity: SCI
• Peripherals: LCD, PWM, WDT
• Number Of I /o: 51
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Timer Mode Register G (TMG)
Note: * Bits 7 and 6 can only be written with 0, for flag clearing.
TMG is an 8-bit read/write register that performs TCG clock selection from four internal clock
sources, counter clear selection, and edge selection for the input capture input signal interrupt
request, controls enabling of overflow interrupt requests, and also contains the overflow flags.
TMG is initialized to H'00 upon reset.
Bit 7—Timer Overflow Flag H (OVFH)
Bit 7 is a status flag indicating that TCG has overflowed from H'FF to H'00 when the input capture
input signal is high. This flag is set by hardware and cleared by software. It cannot be set by
software.
Bit 7
OVFH
0
1
Bit 6—Timer Overflow Flag L (OVFL)
Bit 6 is a status flag indicating that TCG has overflowed from H'FF to H'00 when the input capture
input signal is low, or in interval operation. This flag is set by hardware and cleared by software.
It cannot be set by software.
Bit 6
OVFL
0
1
Bit:
Initial value:
Read/Write:
Description
Clearing condition:
After reading OVFH = 1, cleared by writing 0 to OVFH
Setting condition:
Set when input capture input signal is high level and TCG overflows from H'FF to H'00
Description
Clearing condition:
After reading OVFL = 1, cleared by writing 0 to OVFL
Setting condition:
Set when TCG overflows from H'FF to H'00 while input capture input signal is high
level or during interval operation
R/(W) *
OVFH
7
0
R/(W) *
OVFL
6
0
OVIE
R/W
5
0
IIEGS
R/W
4
0
Rev. 8.00 Mar. 09, 2010 Page 287 of 658
CCLR1
R/W
3
0
CCLR0
R/W
2
0
CKS1
REJ09B0042-0800
R/W
Section 9 Timers
1
0
(initial value)
(initial value)
CKS0
R/W
0
0