HD64F38024DV Renesas Electronics America, HD64F38024DV Datasheet - Page 54

IC H8/SLP MCU FLASH 80QFP

HD64F38024DV

Manufacturer Part Number
HD64F38024DV
Description
IC H8/SLP MCU FLASH 80QFP
Manufacturer
Renesas Electronics America
Series
H8® H8/300L SLPr
Datasheets

Specifications of HD64F38024DV

Core Processor
H8/300L
Core Size
8-Bit
Speed
10MHz
Connectivity
SCI
Peripherals
LCD, PWM, WDT
Number Of I /o
51
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
80-QFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
HD64F38024DV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Section 2 CPU
2.4
2.4.1
The H8/300L CPU supports the eight addressing modes listed in table 2.1. Each instruction uses a
subset of these addressing modes.
Table 2.1
Register Direct—Rn: The register field of the instruction specifies an 8- or 16-bit general register
containing the operand.
Only the MOV.W, ADD.W, SUB.W, CMP.W, ADDS, SUBS, MULXU (8 bits × 8 bits), and
DIVXU (16 bits ÷ 8 bits) instructions have 16-bit operands.
Register Indirect—@Rn: The register field of the instruction specifies a 16-bit general register
containing the address of the operand in memory.
Register Indirect with Displacement—@(d:16, Rn): The instruction has a second word (bytes 3
and 4) containing a displacement which is added to the contents of the specified general register to
obtain the operand address in memory.
This mode is used only in MOV instructions. For the MOV.W instruction, the resulting address
must be even.
Rev. 8.00 Mar. 09, 2010 Page 32 of 658
REJ09B0042-0800
No.
1
2
3
4
5
6
7
8
Addressing Modes
Addressing Modes
Addressing Modes
Address Modes
Register direct
Register indirect
Register indirect with displacement
Register indirect with post-increment
Register indirect with pre-decrement
Absolute address
Immediate
Program-counter relative
Memory indirect
Symbol
Rn
@Rn
@(d:16, Rn)
@Rn+
@–Rn
@aa:8 or @aa:16
#xx:8 or #xx:16
@(d:8, PC)
@@aa:8

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