HD64F38024DV Renesas Electronics America, HD64F38024DV Datasheet - Page 135

• Manufacturer Part Number: HD64F38024DV
• Description: IC H8/SLP MCU FLASH 80QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300L SLPr

Specifications of HD64F38024DV

• Core Processor: H8/300L
• Core Size: 8-Bit
• Speed: 10MHz
• Connectivity: SCI
• Peripherals: LCD, PWM, WDT
• Number Of I /o: 51
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Frequency
Duty
Method for Disabling Subclock Oscillator (H8/38124 Group Only)
The subclock oscillator can be disabled by programs by setting the SUBSTP bit in the OSCCR
register to 1. The register setting to disable the subclock oscillator should be made in the active
mode. When restoring operation of the subclock oscillator after it has been disabled using the
OSCCR register, it is necessary to wait for the oscillation stabilization time (typ: 8s) to elapse
before using the subclock.
4.4
The H8/38024 Group is equipped with two on-chip prescalers having different input clocks
(prescaler S and prescaler W). Prescaler S is a 13-bit counter using the system clock (φ) as its
input clock. Its prescaled outputs provide internal clock signals for on-chip peripheral modules.
Prescaler W is a 5-bit counter using a 32.768 kHz or 38.4 kHz signal divided by 4 (φ
input clock. Its prescaled outputs are used by timer A as a time base for timekeeping.
Prescaler S (PSS)
Prescaler S is a 13-bit counter using the system clock (φ) as its input clock. It is incremented once
per clock period.
Prescaler S is initialized to H'0000 by a reset, and starts counting on exit from the reset state.
In standby mode, watch mode, subactive mode, and subsleep mode, the system clock pulse
generator stops. Prescaler S also stops and is initialized to H'0000.
The CPU cannot read or write prescaler S.
The output from prescaler S is shared by timer A, timer C, timer F, timer G, SCI3, the A/D
converter, the LCD controller, watchdog timer, and the 10-bit PWM. The divider ratio can be set
separately for each on-chip peripheral function.
In active (medium-speed) mode the clock input to prescaler S is φosc/16, φosc/32, φosc/64, or
φosc/128.
Prescalers
Subclock (φw)
45% to 55%
Rev. 8.00 Mar. 09, 2010 Page 113 of 658
Section 4 Clock Pulse Generators
REJ09B0042-0800
W
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