HD64F38024DV Renesas Electronics America, HD64F38024DV Datasheet - Page 382

• Manufacturer Part Number: HD64F38024DV
• Description: IC H8/SLP MCU FLASH 80QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300L SLPr

Specifications of HD64F38024DV

• Core Processor: H8/300L
• Core Size: 8-Bit
• Speed: 10MHz
• Connectivity: SCI
• Peripherals: LCD, PWM, WDT
• Number Of I /o: 51
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 10 Serial Communication Interface
Interrupts and Continuous Transmission/Reception
SCI3 can carry out continuous reception using RXI and continuous transmission using TXI.
These interrupts are shown in table 10.10.
Table 10.10 Transmit/Receive Interrupts
Interrupt
RXI
TXI
TEI
Rev. 8.00 Mar. 09, 2010 Page 360 of 658
REJ09B0042-0800
Flags
RDRF
RIE
TDRE
TIE
TEND
TEIE
Interrupt Request Conditions
When serial reception is performed
normally and receive data is transferred
from RSR to RDR, bit RDRF is set to 1,
and if bit RIE is set to 1 at this time, RXI
is enabled and an interrupt is requested.
(See figure 10.2(a).)
When TSR is found to be empty (on
completion of the previous transmission)
and the transmit data placed in TDR is
transferred to TSR, bit TDRE is set to 1.
If bit TIE is set to 1 at this time, TXI is
enabled and an interrupt is requested.
(See figure 10.2(b).)
When the last bit of the character in
TSR is transmitted, if bit TDRE is set to
1, bit TEND is set to 1. If bit TEIE is set
to 1 at this time, TEI is enabled and an
interrupt is requested. (See figure
10.2(c).)
The RXI interrupt routine reads the
receive data transferred to RDR and
clears bit RDRF to 0. Continuous
reception can be performed by
repeating the above operations until
reception of the next RSR data is
completed.
The TXI interrupt routine writes the
next transmit data to TDR and clears
bit TDRE to 0. Continuous
transmission can be performed by
repeating the above operations until
the data transferred to TSR has
been transmitted.
TEI indicates that the next transmit
data has not been written to TDR
when the last bit of the transmit
character in TSR is sent.
Notes