HD64F38024DV Renesas Electronics America, HD64F38024DV Datasheet - Page 349

• Manufacturer Part Number: HD64F38024DV
• Description: IC H8/SLP MCU FLASH 80QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300L SLPr

Specifications of HD64F38024DV

• Core Processor: H8/300L
• Core Size: 8-Bit
• Speed: 10MHz
• Connectivity: SCI
• Peripherals: LCD, PWM, WDT
• Number Of I /o: 51
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

IRQAEC Operation
When ECPWME in AEGSR is 0, the ECH and ECL input clocks are enabled only when IRQAEC
is high. When IRQAEC is low, the input clocks are not input to the counters, and so ECH and
ECL do not count. ECH and ECL count operations can therefore be controlled from outside by
controlling IRQAEC. In this case, ECH and ECL cannot be controlled individually.
IRQAEC can also operate as an interrupt source. In this case the vector number is 6 and the vector
addresses are H'000C and H'000D.
Interrupt enabling is controlled by IENEC2 in IENR1. When an IRQAEC interrupt is generated,
IRR1 interrupt request flag IRREC2 is set to 1. If IENEC2 in IENR1 is set to 1 at this time, an
interrupt request is sent to the CPU.
Rising, falling, or both edge sensing can be selected for the IRQAEC input pin, with bits AIAGS1
and AIAGS0 in AEGSR.
Note: On the H8/38124 Group, control of switching between the system clock oscillator and the
Event Counter PWM Operation
When ECPWME in AEGSR is 1, the ECH and ECL input clocks are enabled only when event
counter PWM output (IECPWM) is high. When IECPWM is low, the input clocks are not input to
the counters, and so ECH and ECL do not count. ECH and ECL count operations can therefore be
controlled cyclically from outside by controlling event counter PWM. In this case, ECH and ECL
cannot be controlled individually.
IECPWM can also operate as an interrupt source. In this case the vector number is 6 and the
vector addresses are H'000C and H'000D.
Interrupt enabling is controlled by IENEC2 in IENR1. When an IECPWM interrupt is generated,
IRR1 interrupt request flag IRREC2 is set to 1. If IENEC2 in IENR1 is set to 1 at this time, an
interrupt request is sent to the CPU.
Rising, falling, or both edge detection can be selected for IECPWM interrupt sensing with bits
AIAGS1 and AIAGS0 in AEGSR.
on-chip oscillator during resets should be performed by setting the IRQAEC input level.
Refer to section 4, Clock Pulse Generators, for details.
Rev. 8.00 Mar. 09, 2010 Page 327 of 658
REJ09B0042-0800
Section 9 Timers