HD64F38024DV Renesas Electronics America, HD64F38024DV Datasheet - Page 372

• Manufacturer Part Number: HD64F38024DV
• Description: IC H8/SLP MCU FLASH 80QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300L SLPr

Specifications of HD64F38024DV

• Core Processor: H8/300L
• Core Size: 8-Bit
• Speed: 10MHz
• Connectivity: SCI
• Peripherals: LCD, PWM, WDT
• Number Of I /o: 51
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 10 Serial Communication Interface
10.2.8
BRR is an 8-bit register that designates the transmit/receive bit rate in accordance with the baud
rate generator operating clock selected by bits CKS1 and CKS0 of the serial mode register (SMR).
BRR can be read or written by the CPU at any time.
BRR is initialized to H'FF upon reset, and in standby, module standby, or watch mode.
Table 10.3 shows examples of BRR settings in asynchronous mode. The values shown are for
active (high-speed) mode.
Table 10.3 Examples of BRR Settings for Various Bit Rates (Asynchronous Mode) (1)
Bit Rate
(bit/s)
110
150
200
250
300
600
1200
2400
4800
9600
19200
31250
38400
Rev. 8.00 Mar. 09, 2010 Page 350 of 658
REJ09B0042-0800
Bit
Initial value
Read/Write
Bit Rate Register (BRR)
n
—
—
—
0
—
—
16.4 kHz
N
—
—
—
1
—
—
BRR7
R/W
7
1
Error
(%)
—
—
—
2.5
—
—
BRR6
n
—
—
—
—
—
—
—
—
—
0
0
0
0
R/W
6
1
19.2 kHz
—
—
—
N
—
3
2
—
1
0
—
—
—
—
BRR5
R/W
Error
(%)
—
0
0
—
0
0
—
—
—
—
—
—
—
5
1
n
2
2
2
3
0
0
0
0
—
—
—
0
—
BRR4
R/W
4
1
1 MHz
N
12
9
1
103 0.16
51
—
—
—
0
—
17
25
12
φ
—
0
—
Error
(%)
–1.36 2
0.16
–2.34 3
–2.34 0
0.16
0.16
0.16
—
—
BRR3
R/W
3
1
n
3
3
3
2
2
0
0
0
—
0
1.2288 MHz
BRR2
R/W
N
21
3
2
153 –0.26 2
1
0
1
0
7
3
1
—
0
2
1
Error
(%)
–0.83 3
0
0
0
0
0
0
0
0
0
—
0
BRR1
R/W
1
1
n
2
3
2
0
0
0
0
—
—
0
—
2 MHz
N
8
25
4
15
12
103 0.16
51
25
12
—
—
1
—
BRR0
R/W
0
1
Error
(%)
–1.36
0.16
–2.34
–2.34
0.16
0.16
0.16
0.16
—
—
0
—