HD64F38024DV Renesas Electronics America, HD64F38024DV Datasheet - Page 398

IC H8/SLP MCU FLASH 80QFP

HD64F38024DV

Manufacturer Part Number
HD64F38024DV
Description
IC H8/SLP MCU FLASH 80QFP
Manufacturer
Renesas Electronics America
Series
H8® H8/300L SLPr
Datasheets

Specifications of HD64F38024DV

Core Processor
H8/300L
Core Size
8-Bit
Speed
10MHz
Connectivity
SCI
Peripherals
LCD, PWM, WDT
Number Of I /o
51
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
80-QFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
HD64F38024DV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Section 10 Serial Communication Interface
SCI3 operates as follows when receiving data.
SCI3 performs internal synchronization and begins reception in synchronization with the serial
clock input or output.
The received data is placed in RSR in LSB-to-MSB order.
After the data has been received, SCI3 checks that bit RDRF is set to 0, indicating that the receive
data can be transferred from RSR to RDR.
If this check shows that there is no overrun error, bit RDRF is set to 1, and the receive data is
stored in RDR. If bit RIE is set to 1 in SCR3, an RXI interrupt is requested. If the check
identifies an overrun error, bit OER is set to 1.
Bit RDRF remains set to 1. If bit RIE is set to 1 in SCR3, an ERI interrupt is requested.
See table 10.12 for the conditions for detecting a receive error, and receive data processing.
Note: No further receive operations are possible while a receive error flag is set. Bits OER,
Figure 10.14 shows an example of the operation when receiving in synchronous mode.
Rev. 8.00 Mar. 09, 2010 Page 376 of 658
REJ09B0042-0800
RDRF
OER
LSI
operation
User
processing
Serial
clock
Serial
data
FER, PER, and RDRF must therefore be cleared to 0 before resuming reception.
Figure 10.14 Example of Operation when Receiving in Synchronous Mode
RXI request
Bit 7
Bit 0
RDRE cleared
to 0
RDR data read
1 frame
Bit 7
RXI request
Bit 0
Bit 1
1 frame
RDR data has
not been read
(RDRF = 1)
Bit 6
ERI request in
response to
overrun error
Overrun error
processing
Bit 7

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