HD64F38024DV Renesas Electronics America, HD64F38024DV Datasheet - Page 394
HD64F38024DV
Manufacturer Part Number
HD64F38024DV
Description
IC H8/SLP MCU FLASH 80QFP
Manufacturer
Renesas Electronics America
Series
H8® H8/300L SLPr
Datasheets
1.US38024-BAG1.pdf
(684 pages)
2.DF36012GFYV.pdf
(1021 pages)
3.DF38102HV.pdf
(145 pages)
Specifications of HD64F38024DV
Core Processor
H8/300L
Core Size
8-Bit
Speed
10MHz
Connectivity
SCI
Peripherals
LCD, PWM, WDT
Number Of I /o
51
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
80-QFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
HD64F38024DV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
- Current page: 394 of 684
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Section 10 Serial Communication Interface
Data Transfer Format
The general data transfer format in asynchronous communication is shown in figure 10.10.
In synchronous communication, data on the communication line is output from one falling edge of
the serial clock until the next falling edge. Data confirmation is guaranteed at the rising edge of
the serial clock.
One transfer data character begins with the LSB and ends with the MSB. After output of the
MSB, the communication line retains the MSB state.
When receiving in synchronous mode, SCI3 latches receive data at the rising edge of the serial
clock.
The data transfer format uses a fixed 8-bit data length.
Parity bit cannot be added.
Clock
Either an internal clock generated by the baud rate generator or an external clock input at the
SCK
SMR and bits CKE1 and CKE0 in SCR3. See table 10.9 for details on clock source selection.
When SCI3 operates on an internal clock, the serial clock is output at the SCK
of the serial clock are output in transmission or reception of one character, and when SCI3 is not
transmitting or receiving, the clock is fixed at the high level.
Rev. 8.00 Mar. 09, 2010 Page 372 of 658
REJ09B0042-0800
Serial
clock
Serial
data
32
pin can be selected as the SCI3 serial clock. The selection is made by means of bit COM in
Note: * High level except in continuous transmission/reception
Don't
care
*
LSB
Figure 10.10 Data Format in Synchronous Communication
Bit 0
Bit 1
One transfer data unit (character or frame)
Bit 2
Bit 3
8 bits
Bit 4
Bit 5
Bit 6
32
pin. Eight pulses
Bit 7
MSB
Don't
care
*
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