HD64F38024DV Renesas Electronics America, HD64F38024DV Datasheet - Page 397

IC H8/SLP MCU FLASH 80QFP

HD64F38024DV

Manufacturer Part Number
HD64F38024DV
Description
IC H8/SLP MCU FLASH 80QFP
Manufacturer
Renesas Electronics America
Series
H8® H8/300L SLPr
Datasheets

Specifications of HD64F38024DV

Core Processor
H8/300L
Core Size
8-Bit
Speed
10MHz
Connectivity
SCI
Peripherals
LCD, PWM, WDT
Number Of I /o
51
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
80-QFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
HD64F38024DV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
• Receiving
Figure 10.13 shows an example of a flowchart for data reception. This procedure should be
followed for data reception after initializing SCI3.
Figure 10.13 Example of Data Reception Flowchart (Synchronous Mode)
Read bit RDRF
Clear bit RE to
Continue data
Read bit OER
Read receive
data in RDR
RDRF = 1?
reception?
0 in SCR3
OER = 1?
in SSR
in SSR
Start
End
No
Yes
No
[3]
[1]
[2]
Overrun error
processing
Yes
No
Yes
4
Clear bit OER to
error processing
error processing
End of overrun
Overrun error
Start overrun
processing
[4]
0 in SSR
[1]
[2]
[3]
[4]
Read bit OER in the serial status register
(SSR) to determine if there is an error.
If an overrun error has occurred, execute
overrun error processing.
Read SSR and check that bit RDRF is
set to 1. If it is, read the receive data in
RDR. When the RDR data is read, bit
RDRF is cleared to 0 automatically.
When continuing data reception, finish
reading of bit RDRF and RDR before
receiving the MSB (bit 7) of the current
frame. When the data in RDR is read,
bit RDRF is cleared to 0 automatically.
If an overrun error has occurred, read bit
OER in SSR, and after carrying out the
necessary error processing, clear bit OER
to 0. Reception cannot be resumed if bit
OER is set to 1.
Section 10 Serial Communication Interface
Rev. 8.00 Mar. 09, 2010 Page 375 of 658
REJ09B0042-0800

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