HD64F38024DV Renesas Electronics America, HD64F38024DV Datasheet - Page 366

• Manufacturer Part Number: HD64F38024DV
• Description: IC H8/SLP MCU FLASH 80QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300L SLPr

Specifications of HD64F38024DV

• Core Processor: H8/300L
• Core Size: 8-Bit
• Speed: 10MHz
• Connectivity: SCI
• Peripherals: LCD, PWM, WDT
• Number Of I /o: 51
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 10 Serial Communication Interface
Bit 4—Receive Enable (RE)
Bit 4 selects enabling or disabling of the start of receive operation.
Bit 4
RE
0
1
Notes: 1. Note that the RDRF, FER, PER, and OER flags in SSR are not affected when bit RE is
Bit 3—Reserved (MPIE)
It’s a reserved bit.
Bit 2—Transmit End Interrupt Enable (TEIE)
Bit 2 selects enabling or disabling of the transmit end interrupt request (TEI) if there is no valid
transmit data in TDR when MSB data is to be sent.
Bit 2
TEIE
0
1
Note: * TEI can be released by clearing bit TDRE to 0 and clearing bit TEND to 0 in SSR, or by
Rev. 8.00 Mar. 09, 2010 Page 344 of 658
REJ09B0042-0800
2. In this state, serial data reception is started when a start bit is detected in asynchronous
clearing bit TEIE to 0.
cleared to 0, and retain their previous state.
mode or serial clock input is detected in synchronous mode. Be sure to carry out serial
mode register (SMR) settings to decide the reception format before setting bit RE to 1.
Description
Receive operation disabled *
Receive operation enabled *
Description
Transmit end interrupt request (TEI) disabled
Transmit end interrupt request (TEI) enabled *
2
1
(RXD32 pin is receive data pin)
(RXD32 pin is I/O port)
(initial value)
(initial value)