HD64F38024DV Renesas Electronics America, HD64F38024DV Datasheet - Page 314

• Manufacturer Part Number: HD64F38024DV
• Description: IC H8/SLP MCU FLASH 80QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300L SLPr

Specifications of HD64F38024DV

• Core Processor: H8/300L
• Core Size: 8-Bit
• Speed: 10MHz
• Connectivity: SCI
• Peripherals: LCD, PWM, WDT
• Number Of I /o: 51
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 9 Timers
9.5.4
Timer G is an 8-bit timer with built-in input capture and interval functions.
Timer G Functions
Timer G is an 8-bit up-counter with two functions, an input capture timer function and an interval
timer function.
The operation of these two functions is described below.
a. Input capture timer operation
Rev. 8.00 Mar. 09, 2010 Page 292 of 658
REJ09B0042-0800
When the TMIG bit in port mode register 1 (PMR1) is set to 1, timer G functions as an input
capture timer * .
In a reset, timer mode register G (TMG), timer counter G (TCG), input capture register GF
(ICRGF), and input capture register GR (ICRGR) are all initialized to H'00.
Following a reset, TCG starts counting on the φ/64 internal clock.
The input clock can be selected from four internal clock sources by bits CKS1 and CKS0 in
TMG.
When a rising edge/falling edge is detected in the input capture signal input from the TMIG
pin, the TCG value at that time is transferred to ICRGR/ICRGF. When the edge selected by
IIEGS in TMG is input, IRRTG in IRR2 is set to 1, and if the IENTG bit in IENR2 is 1 at this
time, an interrupt request is sent to the CPU. For details of the interrupt, see section 3.3,
Interrupts.
TCG can be cleared by a rising edge, falling edge, or both edges of the input capture signal,
according to the setting of bits CCLR1 and CCLR0 in TMG. If TCG overflows when the
input capture signal is high, the OVFH bit in TMG is set; if TCG overflows when the input
capture signal is low, the OVFL bit in TMG is set. If the OVIE bit in TMG is 1 when these
bits are set, IRRTG in IRR2 is set to 1, and if the IENTG bit in IENR2 is 1, timer G sends an
interrupt request to the CPU. For details of the interrupt, see section 3.3, Interrupts.
Timer G has a built-in noise canceler that enables high-frequency component noise to be
eliminated from pulses input from the TMIG pin. For details, see section 9.5.3, Noise
Canceler.
Note: * An input capture signal may be generated when TMIG is modified.
Operation