HD64F38024DV Renesas Electronics America, HD64F38024DV Datasheet - Page 362

• Manufacturer Part Number: HD64F38024DV
• Description: IC H8/SLP MCU FLASH 80QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300L SLPr

Specifications of HD64F38024DV

• Core Processor: H8/300L
• Core Size: 8-Bit
• Speed: 10MHz
• Connectivity: SCI
• Peripherals: LCD, PWM, WDT
• Number Of I /o: 51
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 10 Serial Communication Interface
Bit 5—Parity Enable (PE)
Bit 5 selects whether a parity bit is to be added during transmission and checked during reception
in asynchronous mode. In synchronous mode parity bit addition and checking is not performed,
irrespective of the bit 5 setting.
Bit 5
PE
0
1
Notes: 1. When PE is set to 1, even or odd parity, as designated by bit PM, is added to transmit
Bit 4—Parity Mode (PM)
Bit 4 selects whether even or odd parity is to be used for parity addition and checking. The PM bit
setting is only valid in asynchronous mode when bit PE is set to 1, enabling parity bit addition and
checking. The PM bit setting is invalid in synchronous mode, and in asynchronous mode if parity
bit addition and checking is disabled.
Bit 4
PM
0
1
Notes: 1. When even parity is selected, a parity bit is added in transmission so that the total
Rev. 8.00 Mar. 09, 2010 Page 340 of 658
REJ09B0042-0800
2. For the case where 5-bit data is selected, see table 10.11.
2. When odd parity is selected, a parity bit is added in transmission so that the total
data before it is sent, and the received parity bit is checked against the parity
designated by bit PM.
number of 1 bits in the transmit data plus the parity bit is an even number; in reception,
a check is carried out to confirm that the number of 1 bits in the receive data plus the
parity bit is an even number.
number of 1 bits in the transmit data plus the parity bit is an odd number; in reception, a
check is carried out to confirm that the number of 1 bits in the receive data plus the
parity bit is an odd number.
Description
Parity bit addition and checking disabled *
Parity bit addition and checking enabled *
Description
Even parity *
Odd parity *
2
1
1/
2
*
2
(initial value)
(initial value)