HD64F38024DV Renesas Electronics America, HD64F38024DV Datasheet - Page 143

• Manufacturer Part Number: HD64F38024DV
• Description: IC H8/SLP MCU FLASH 80QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300L SLPr

Specifications of HD64F38024DV

• Core Processor: H8/300L
• Core Size: 8-Bit
• Speed: 10MHz
• Connectivity: SCI
• Peripherals: LCD, PWM, WDT
• Number Of I /o: 51
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

5.1
The LSI has nine modes of operation after a reset. These include eight power-down modes, in
which power dissipation is significantly reduced. Table 5.1 gives a summary of the nine operating
modes.
Table 5.1
Operating Mode
Active (high-speed) mode
Active (medium-speed) mode
Subactive mode
Sleep (high-speed) mode
Sleep (medium-speed) mode
Subsleep mode
Watch mode
Standby mode
Module standby mode
Of these nine operating modes, all but the active (high-speed) mode are power-down modes. In
this section the two active modes (high-speed and medium speed) will be referred to collectively
as active mode.
Figure 5.1 shows the transitions among these operation modes. Table 5.2 indicates the internal
states in each mode.
Overview
Operating Modes
Section 5 Power-Down Modes
Description
The CPU and all on-chip peripheral functions are operable on
the system clock in high-speed operation
The CPU and all on-chip peripheral functions are operable on
the system clock in low-speed operation
The CPU and all on-chip peripheral functions are operable on
the subclock in low-speed operation
The CPU halts. On-chip peripheral functions are operable on
the system clock
The CPU halts. On-chip peripheral functions operate at a
frequency of 1/128, 1/64, 1/32, or 1/16 of the system clock
frequency
The CPU halts. The time-base function of timer A, timer C,
timer F, timer G, SCI3, AEC, and LCD controller/driver are
operable on the subclock
The CPU halts. The time-base function of timer A, timer F,
timer G, AEC and LCD controller/driver are operable on the
subclock
The CPU and all on-chip peripheral functions halt
Individual on-chip peripheral functions specified by software
enter standby mode and halt
Rev. 8.00 Mar. 09, 2010 Page 121 of 658
Section 5 Power-Down Modes
REJ09B0042-0800