HD64F38024DV Renesas Electronics America, HD64F38024DV Datasheet - Page 390

• Manufacturer Part Number: HD64F38024DV
• Description: IC H8/SLP MCU FLASH 80QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300L SLPr

Specifications of HD64F38024DV

• Core Processor: H8/300L
• Core Size: 8-Bit
• Speed: 10MHz
• Connectivity: SCI
• Peripherals: LCD, PWM, WDT
• Number Of I /o: 51
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 10 Serial Communication Interface
• Receiving
Figure 10.8 shows an example of a flowchart for data reception. This procedure should be
followed for data reception after initializing SCI3.
Rev. 8.00 Mar. 09, 2010 Page 368 of 658
REJ09B0042-0800
Figure 10.8 Example of Data Reception Flowchart (Asynchronous Mode)
PER, FER in SSR
Read bit RDRF
Read bits OER,
Clear bit RE to
Continue data
Read receive
OER + PER
data in RDR
+ FER = 1?
RDRF = 1?
reception?
0 in SCR3
in SSR
Start
End
No
Yes
No
[3]
Receive error
[1]
[2]
processing
Yes
No
Yes
(A)
[4]
[1]
[2]
[3]
Read bits OER, PER, and FER in the
serial status register (SSR) to determine
if there is an error. If a receive error has
occurred, execute receive error
processing.
Read SSR and check that bit RDRF is
set to 1. If it is, read the receive data
in RDR. When the RDR data is read,
bit RDRF is cleared to 0 automatically.
reading of bit RDRF and RDR before
receiving the stop bit of the current
frame. When the data in RDR is read,
bit RDRF is cleared to 0 automatically.
When continuing data reception, finish