HD64F38024DV Renesas Electronics America, HD64F38024DV Datasheet - Page 305

IC H8/SLP MCU FLASH 80QFP

HD64F38024DV

Manufacturer Part Number
HD64F38024DV
Description
IC H8/SLP MCU FLASH 80QFP
Manufacturer
Renesas Electronics America
Series
H8® H8/300L SLPr
Datasheets

Specifications of HD64F38024DV

Core Processor
H8/300L
Core Size
8-Bit
Speed
10MHz
Connectivity
SCI
Peripherals
LCD, PWM, WDT
Number Of I /o
51
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
80-QFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
HD64F38024DV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
9.5
9.5.1
Timer G is an 8-bit timer with dedicated input capture functions for the rising/falling edges of
pulses input from the input capture input pin (input capture input signal). High-frequency
component noise in the input capture input signal can be eliminated by a noise canceler, enabling
accurate measurement of the input capture input signal duty cycle. If input capture input is not set,
timer G functions as an 8-bit interval timer.
Features
Features of timer G are given below.
• Choice of four internal clock sources (φ/64, φ/32, φ/2, φw/4)
• Dedicated input capture functions for rising and falling edges
• Level detection at counter overflow
• Selection of whether or not the counter value is to be cleared at the input capture input signal
• Two interrupt sources: one input capture, one overflow. The input capture input signal rising
• A built-in noise canceler eliminates high-frequency component noise in the input capture input
• Watch mode, subactive mode, or subsleep mode operation is possible when φw/4 is selected as
• Use of module standby mode enables this module to be placed in standby mode independently
It is possible to detect whether overflow occurred when the input capture input signal was high
or when it was low.
rising edge, falling edge, or both edges
or falling edge can be selected as the interrupt source.
signal.
the internal clock.
when not used.
Timer G
Overview
Rev. 8.00 Mar. 09, 2010 Page 283 of 658
REJ09B0042-0800
Section 9 Timers

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