HD64F38024DV Renesas Electronics America, HD64F38024DV Datasheet - Page 343

IC H8/SLP MCU FLASH 80QFP

HD64F38024DV

Manufacturer Part Number
HD64F38024DV
Description
IC H8/SLP MCU FLASH 80QFP
Manufacturer
Renesas Electronics America
Series
H8® H8/300L SLPr
Datasheets

Specifications of HD64F38024DV

Core Processor
H8/300L
Core Size
8-Bit
Speed
10MHz
Connectivity
SCI
Peripherals
LCD, PWM, WDT
Number Of I /o
51
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
80-QFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
HD64F38024DV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Event Counter Control/Status Register (ECCSR)
ECCSR is an 8-bit read/write register that controls counter overflow detection, counter resetting,
and halting of the count-up function.
ECCSR is initialized to H'00 upon reset.
Bit 7—Counter Overflow H (OVH)
Bit 7 is a status flag indicating that ECH has overflowed from H'FF to H'00. This flag is set when
ECH overflows. It is cleared by software but cannot be set by software. OVH is cleared by
reading it when set to 1, then writing 0.
When ECH and ECL are used as a 16-bit event counter with CH2 cleared to 0, OVH functions as a
status flag indicating that the 16-bit event counter has overflowed from H'FFFF to H'0000.
Bit 7
OVH
0
1
Bit 6—Counter Overflow L (OVL)
Bit 6 is a status flag indicating that ECL has overflowed from H'FF to H'00. This flag is set when
ECL overflows. It is cleared by software but cannot be set by software. OVL is cleared by
reading it when set to 1, then writing 0.
Bit
Initial Value
Read/Write
Note:
*
Bits 7 and 6 can only be written with 0, for flag clearing.
Description
ECH has not overflowed
Clearing condition:
After reading OVH = 1, cleared by writing 0 to OVH
ECH has overflowed
Setting condition:
Set when ECH overflows from H’FF to H’00
R/W *
OVH
0
7
R/W *
OVL
0
6
R/W
0
5
CH2
R/W
4
0
Rev. 8.00 Mar. 09, 2010 Page 321 of 658
CUEH
R/W
0
3
CUEL
R/W
2
0
REJ09B0042-0800
CRCH
Section 9 Timers
R/W
0
1
(initial value)
CRCL
R/W
0
0

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