HD64F38024DV Renesas Electronics America, HD64F38024DV Datasheet - Page 333

• Manufacturer Part Number: HD64F38024DV
• Description: IC H8/SLP MCU FLASH 80QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300L SLPr

Specifications of HD64F38024DV

• Core Processor: H8/300L
• Core Size: 8-Bit
• Speed: 10MHz
• Connectivity: SCI
• Peripherals: LCD, PWM, WDT
• Number Of I /o: 51
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

9.6.3
The watchdog timer has an 8-bit counter (TCW) that is incremented by clock input. The input
clock is selected by the WDCKS in port mode register 2 (PMR2): on the H8/38024, H8/38024S,
and H8/38024R Group, φ/8192 is selected when WDCKS is cleared to 0, and φw/32 when set to 1.
On the H8/38124 Group, if WDCKS is cleared to 0 the clock selection is specified by the setting
of timer mode register W (TMW), and if WDCKS is set to 1 the φw/32 clock source is selected.
When TCSRWE = 1 in TCSRW, if 0 is written in B2WI and 1 is simultaneously written in
WDON, TCW starts counting up. (Write access to TCSRW is required twice to turn on the
watchdog timer. However, on the H8/38124 Group WDON is set to 1 after a reset is cancelled,
TCW starts to be incremented even without gaining write access to TCSRW.) When the TCW
count value reaches H'FF, the next clock input causes the watchdog timer to overflow, and an
internal reset signal is generated one base clock (φ or φ
output for 512 clock cycles of the φ
count up from the written value. The overflow period can be set in the range from 1 to 256 input
clocks, depending on the value written in TCW.
Figure 9.18 shows an example of watchdog timer operations.
Timer Operation
Internal reset
signal
TCW count
value
H'FF
H'00
Figure 9.18 Typical Watchdog Timer Operations (Example)
Example: φ = 2 MHz and the desired overflow period is 30 ms.
The value set in TCW should therefore be 256 − 8 = 248 (H'F8).
H'F8
H'F8 is written
in TCW
2 • 10
8192
Start
OSC
6
• 30 • 10
clock. It is possible to write to TCW, causing TCW to
H'F8 is written in TCW
−3
= 7.3
SUB
Rev. 8.00 Mar. 09, 2010 Page 311 of 658
) cycle later. The internal reset signal is
512 φ
OSC
Reset
TCW overflow
clock cycles
REJ09B0042-0800
Section 9 Timers