HD64F38024DV Renesas Electronics America, HD64F38024DV Datasheet - Page 77

• Manufacturer Part Number: HD64F38024DV
• Description: IC H8/SLP MCU FLASH 80QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300L SLPr

Specifications of HD64F38024DV

• Core Processor: H8/300L
• Core Size: 8-Bit
• Speed: 10MHz
• Connectivity: SCI
• Peripherals: LCD, PWM, WDT
• Number Of I /o: 51
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

2.6
CPU operation is synchronized by a system clock (φ) or a subclock (φ
clock signals see section 4, Clock Pulse Generators. The period from a rising edge of φ or φ
the next rising edge is called one state. A bus cycle consists of two states or three states. The
cycle differs depending on whether access is to on-chip memory or to on-chip peripheral modules.
2.6.1
Access to on-chip memory takes place in two states. The data bus width is 16 bits, allowing
access in byte or word size. Figure 2.11 shows the on-chip memory access cycle.
φ or φ
Internal address bus
Internal read signal
Internal data bus
(read access)
Internal write signal
Internal data bus
(write access)
Access to On-Chip Memory (RAM, ROM)
Basic Operational Timing
SUB
Figure 2.11 On-Chip Memory Access Cycle
T
1
state
Bus cycle
Address
Rev. 8.00 Mar. 09, 2010 Page 55 of 658
Write data
Read data
T
2
state
SUB
). For details on these
REJ09B0042-0800
Section 2 CPU
SUB
to