HD64F38024DV Renesas Electronics America, HD64F38024DV Datasheet - Page 399

• Manufacturer Part Number: HD64F38024DV
• Description: IC H8/SLP MCU FLASH 80QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300L SLPr

Specifications of HD64F38024DV

• Core Processor: H8/300L
• Core Size: 8-Bit
• Speed: 10MHz
• Connectivity: SCI
• Peripherals: LCD, PWM, WDT
• Number Of I /o: 51
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

• Simultaneous transmit/receive
Figure 10.15 shows an example of a flowchart for a simultaneous transmit/receive operation. This
procedure should be followed for simultaneous transmission/reception after initializing SCI3.
Figure 10.15 Example of Simultaneous Data Transmission/Reception Flowchart
transmission/reception?
Read receive data
Clear bits TE and
Sets bit SPC32 to
RE to 0 in SCR3
Read bit TDRE
Read bit RDRF
Write transmit
Continue data
Read bit OER
data to TDR
TDRE = 1?
RDRF = 1?
1 in SPCR
OER = 1?
in SSR
in RDR
in SSR
in SSR
Start
End
Yes
No
Yes
No
[3]
[2]
[1]
Yes
No
No
Yes
Overrun error
processing
(Synchronous Mode)
[4]
[1]
[2]
[3]
[4]
Read the serial status register (SSR) and
check that bit TDRE is set to 1, then write
transmit data to the transmit data register
(TDR). When data is written to TDR, bit
TDRE is cleared to 0 automatically.
Read SSR and check that bit RDRF is set
to 1. If it is, read the receive data in RDR.
When the RDR data is read, bit RDRF is
cleared to 0 automatically.
When continuing data transmission/reception,
finish reading of bit RDRF and RDR before
receiving the MSB (bit 7) of the current frame.
Before receiving the MSB (bit 7) of the current
frame, also read TDRE = 1 to confirm that a
write can be performed, then write data to TDR.
When data is written to TDR, bit TDRE is cleared
to 0 automatically, and when the data in RDR is
read, bit RDRF is cleared to 0 automatically.
If an overrun error has occurred, read bit OER
in SSR, and after carrying out the necessary
error processing, clear bit OER to 0. Transmis-
sion and reception cannot be resumed if bit
OER is set to 1.
See figure 10.13 for details on overrun error
processing.
Section 10 Serial Communication Interface
Rev. 8.00 Mar. 09, 2010 Page 377 of 658
REJ09B0042-0800