HD64F38024DV Renesas Electronics America, HD64F38024DV Datasheet - Page 289

• Manufacturer Part Number: HD64F38024DV
• Description: IC H8/SLP MCU FLASH 80QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300L SLPr

Specifications of HD64F38024DV

• Core Processor: H8/300L
• Core Size: 8-Bit
• Speed: 10MHz
• Connectivity: SCI
• Peripherals: LCD, PWM, WDT
• Number Of I /o: 51
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

16-bit Output Compare Register (OCRF)
8-bit Output Compare Register (OCRFH)
8-bit Output Compare Register (OCRFL)
Bit:
Initial value:
Read/Write:
OCRF is a 16-bit read/write register composed of the two registers OCRFH and OCRFL. In
addition to the use of OCRF as a 16-bit register with OCRFH as the upper 8 bits and OCRFL as
the lower 8 bits, OCRFH and OCRFL can also be used as independent 8-bit registers.
OCRFH and OCRFL can be read and written by the CPU, but when they are used in 16-bit mode,
data transfer to and from the CPU is performed via a temporary register (TEMP). For details of
TEMP, see section 9.4.3, CPU Interface.
OCRFH and OCRFL are each initialized to H'FF upon reset.
a. 16-bit mode (OCRF)
b. 8-bit mode (OCRFH/OCRFL)
When CKSH2 is cleared to 0 in TCRF, OCRF operates as a 16-bit register. OCRF contents
are constantly compared with TCF, and when both values match, CMFH is set to 1 in TCSRF.
At the same time, IRRTFH is set to 1 in IRR2. If IENTFH in IENR2 is 1 at this time, an
interrupt request is sent to the CPU.
Toggle output can be provided from the TMOFH pin by means of compare matches, and the
output level can be set (high or low) by means of TOLH in TCRF.
When CKSH2 is set to 1 in TCRF, OCRFH, and OCRFL operate as two independent 8-bit
registers. OCRFH contents are compared with TCFH, and OCRFL contents are with TCFL.
When the OCRFH (OCRFL) and TCFH (TCFL) values match, CMFH (CMFL) is set to 1 in
TCSRF. At the same time, IRRTFH (IRRTFL) is set to 1 in IRR2. If IENTFH (IENTFL) in
IENR2 is 1 at this time, an interrupt request is sent to the CPU.
Toggle output can be provided from the TMOFH pin (TMOFL pin) by means of compare
matches, and the output level can be set (high or low) by means of TOLH (TOLL) in TCRF.
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
15
1
14
1
13
1
OCRFH
12
1
11
1
10
1
9
1
8
1
OCRF
Rev. 8.00 Mar. 09, 2010 Page 267 of 658
7
1
6
1
5
1
OCRFL
4
1
3
1
REJ09B0042-0800
Section 9 Timers
2
1
1
1
0
1